Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Display Technologies Corporation

Sharp Kabushiki Kaisha Corporation

Fujitsu Semiconductor Memory Solution Limited

Keizo Morita

Shoichiro Kawashima

Hiroshi Murakami

Munehiro Haraguchi

Koji Yoshioka

Masafumi Itokazu

Isao Fukushi

Ken-ichi Nakabayashi

Tomohisa Hirayama

Hongyong Zhang

Akira Yamamoto

Naoharu Shinozaki

Yasuhiro Fujii

Masaki Aoki

Kazuaki Takai

Mitsuharu Nakazawa

Kenichi Nakabayashi

Kazuaki Yamane

Hirokazu Yamazaki

Mitsuhiro Ogai

Masaki Okuda

A first pre-sense amplifier connected to reference cells that hold data of logical value '1' via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

Semiconductor storage device, read method thereof, and test method thereof

Semiconductor storage device and read method thereof

A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Ferroelectric memory device and timing circuit to control the boost level of a word line

A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of '1's in each of the rows is an even number.

Ferroelectric memory device

A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.

Semiconductor device and system

A voltage detection circuit outputs a detection signal when an amount of charges read to one of a pair of bit lines reaches a predetermined amount. A mask circuit of a timing generator masks an output of a sense amplifier activation signal until the detection signal is output. A sense amplifier determines logics of data read to the bit lines from memory cells in synchronization with the sense amplifier activation signal. An operation of the sense amplifier is started after predetermined amounts of charges are read from the memory cells to the bit lines, that is, after the detection signal is output. Accordingly, even when a timing to output a timing signal becomes early due to a variance of manufacturing conditions of a semiconductor memory, data read from the memory cells can be latched correctly in the sense amplifier. As a result, malfunctions of the semiconductor memory can be prevented.

Semiconductor memory including voltage detection circuit for generating sense amplifier signal

A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.

Semiconductor storage device using a bitline GND sensing scheme for a reduced real estate of pre-sense amplifier

A memory device includes a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.

Memory device

A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.

Semiconductor memory

The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected, the potential of normal bit lines and of reference bit line changes according to the charge on the storage capacitors and on the reference capacitor. A current mirror circuit is also provided, which has a first transistor drain of which is connected to the reference bit line and second transistors drains of which are respectively connected to normal bit lines, the gates of the first and second transistors being connected in common to the reference bit line. Thus even though the capacitance values of ferroelectric capacitors is scattered, the scattering in bit line potentials during read operations can be prevented.

A display device has a display section having scanning lines, and first and second scanning drivers having output lines for supplying scanning signals to the two ends of the scanning lines in the display section. When the potential of at least one of the output lines of the first or second scanning driver is fixed or unfixed due to an error in the first or second scanning driver, the output line at the fixed or unfixed potential is disconnected from the corresponding scanning line in the display section.

Display device and driving method of the same

A stacked FeRAM uses a structure where the bit line is formed above the ferroelectric capacitor. The word line is formed so that it moves away from the opposing other word line in areas near the contact plug with the relevant contact plug in between, and moves toward the other word line in areas not near the contact plug, and the contact hole is formed so that it is displaced alternately with respect to the longitudinal centerline of the relevant plate line.

Semiconductor device and method of manufacturing the same

A liquid crystal display device has: a first substrate having an insulating surface; a display unit disposed in a central area of the first substrate and including a plurality of pixels disposed in a matrix shape, a plurality of scan lines for activating pixels disposed in a row direction, and a plurality of signal lines each for transferring video data to an activated pixel among pixels disposed in a column direction; a scan line driver circuit formed in a first row direction side area of a peripheral area of the first substrate outside of the display unit, the scan line driver circuit generating a signal for driving the scan lines; a signal line driver circuit formed in a first column direction side area of the peripheral area of the first substrate, the signal line driver circuit generating a signal for driving the signal lines; and a repair circuit formed in a partial area of the peripheral area of the first substrate, the repair circuit having substantially a same structure as a portion of the scan line driver circuit and the signal line driver circuit. A line defect of the display device can be repaired easily.

Repairable LCD and its manufacture

In the semiconductor integrated circuit, an auxiliary conductor is formed in a wiring layer beneath a signal wire which connects a position Vin estimated to generate static electricity and a position Vout to be protected from static electricity. The capacitance of a glass substrate can be reduced to {fraction (1/1000)} of the capacitance of the interlayer insulating film. Accordingly, even if a voltage of 1000 to 2000 V is generated between a substrate conveying system and the auxiliary conductor, the glass substrate works as a dielectric, and the voltage generated between the auxiliary conductor and signal wire is only several volts.

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Kawasaki, Japan

Keizo Morita