Hitachi, Ltd.

Texas Instruments Corporation

Other

Keizo Kawakita

Yoshitaka Tadaki

Hideo Aoki

Toshihiro Sekiguchi

Isamu Asano

Songsu Cho

Michio Nishimura

Katsuo Yuhara

Satoru Yamada

Yoshitaka Nakamura

Tsuyoshi Tamaru

Michio Tanaka

Masayoshi Hirasawa

Jun Murata

Toshiyuki Kaeriyama

Naoki Fukuda

Hidekazu Goto

Kazuhiko Saitoh

Yuji Ezaki

Hiroshi Sakuma

Katsuhiko Tanaka

Takuya Fukuda

Shinya Nishio

Toshikazu Kumai

Hiroyuki Uchiyama

Norio Hasegawa

Makoto Yoshida

Masayuki Suzuki

Masayoshi Saito

Takahiro Kumauchi

Minoru Ohtsuka

Kazuhiko Saito

Masayuki Yasuda

Takashi Hayakawa

Kazuhiko Kajigaya

Kazunari Suzuki

Seiji Narui

Takeshi Sakai

Kiyoshi Nakai

Takafumi Tokunaga

Kiyomi Katsuyama

Hisao Asakura

Hideaki Tsugane

Akihiko Konno

Takatoshi Kakizaki

Fumiyoshi Sato

Hideo Nagasawa

Fumiaki Saitoh

Katsutoshi Matsunaga

Yoshimi Torii

The semiconductor device is formed according to the following steps. A TiN filmand a W filmare deposited on a silicon oxide filmincluding the inside of a via-holeby the CVD method and thereafter, the W filmand TiN filmon the silicon oxide filmare etched back to leave only the inside of the via-holeand form a plug. Then, a TiN film, Al-alloy film, and Ti filmare deposited on the silicon oxide filmincluding the surface of the plugby the sputtering method and thereafter, the Ti film, Al-alloy film, and TiN filmare patterned to form second-layer wiringsand

Semiconductor integrated circuit device having a conductive film which contains metal atoms bondable to a halogen element

An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (). The memory-cell selection MISFET (Qs) has an insulated gate electrode () (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate () with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode () (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate () with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

Semiconductor integrated circuit device and manufacturing method thereof

A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

Method for fabricating semiconductor integrated circuit

An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate ( ). The memory-cell selection MISFET (Qs) has an insulated gate electrode ( ) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate ( ) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode ( ) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width. In addition, a bit line (BL) is provided overlying the memory-cell select MISFET (Qs) in a manner such that the bit line extends in the X direction on the principal surface of the semiconductor substrate ( ) with the same width and opposes its neighboring bit line (BL) at a distance or pitch that is wider than said width.

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film , the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing a semiconductor integrated circuit device having a capacitor

The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

The semiconductor device is formed according to the following steps. A TiN film and a W film are deposited on a silicon oxide film including the inside of a via-hole by the CVD method and thereafter, the W film and TiN film on the silicon oxide film are etched back to leave only the inside of the via-hole and form a plug . Then, a TiN film , Al-alloy film , and Ti film are deposited on the silicon oxide film including the surface of the plug by the sputtering method and thereafter, the Ti film , Al-alloy film , and TiN film are patterned to form second-layer wirings and

Semiconductor integrated circuit and method of fabricating the same

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta O (tantalum oxide) film the portions of bit lines BL and first-layer interconnect lines to of a peripheral circuit which are in contact with at least an underlying silicon oxide film are formed of a W film, the bit lines BL and the interconnect lines to being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines to and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Method of manufacturing semiconductor integrated circuit device having a capacitor

A pattern of more than one conductive layer overlying a fuse formed in a TEG region is subject to OR processing; further, a combined or &ldquo;synthetic&rdquo; pattern with an opening pattern of one or more testing pads connected to said fuse added thereto is copied by transfer printing techniques to a photosensitive resin layer that is coated on the surface of a semiconductor wafer, thereby forcing the resin layer to reside only in a selected area of a scribe region, to which area the synthetic pattern has been transferred.

Semiconductor integrated circuit device and method for production of the same

In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.

Semiconductor integrated circuit device and method of manufacturing the same

In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta,O,(tantalum oxide) film,the portions of bit lines BL and first-layer interconnect lines,to,of a peripheral circuit which are in contact with at least an underlying silicon oxide film,are formed of a W film, the bit lines BL and the interconnect lines,to,being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines,to,and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.

Semiconductor integrated circuit device, and method of manufacturing the same

A method of making semiconductor devices which enables control of the impurity concentration and fine patterning by making removal of residual stress due LOCOS oxidation compatible with the formation of deep wells. A selective oxide layer is formed for separating element regions on a principal plane of a semiconductor substrate, for example, a p.sup.- -type silicon substrate 1. A mask is formed (for example photoresist 47) on the surface including the selective oxide layer and impurities (for example phosphorous) of a conductivity type opposite that of the semiconductor substrate are introduced via an opening in the mask. Then the selective oxide film is annealed by a high-temperature treatment while a deep well (for example n-type deep well 50) is formed by introducing the impurities.

Method of manufacturing semiconductor device

Growing community of inventors

Ome, Japan

Keizo Kawakita