Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Keizo Aoyagi

Yukio Shiraogawa

Tsutomu Sakamoto

Michio Arai

Takashi Rokutanda

Jyun-ichi Kihara

Yutaka Nakajima

Morishige Kinjo

Takashi Hiraoka

A main memory has a plurality of divided storage areas. A central processing unit saves data from each storage area of the main memory into an auxiliary memory during a normal operation of a computer system, and sets a flag corresponding to each storage area, from which the data is saved, in a state indicating the end of a save operation. In addition, when data stored in the main memory is updated, the central processing unit changes the flag into a state indicating an incomplete save state. When the computer system must be stopped, the central processing unit saves data, of the data stored in the main memory, only from a storage area for which the flag indicates an incomplete save state into the auxiliary memory, thereby shortening the time required for save processing.

Data processing system having selective data save and address

A high speed address calculation circuit for a pipeline-control-system data-processing apparatus includes an instruction register, a register file, an address register, a first data selector, an increment register, a second data selector, a decoder, an adder and a third data selector. The instruction register stores instructions from a memory, and the register file is addressed by the register designation data of the instructions stored in the instruction register. The address register stores an operand address, and the increment register stores increment data calculated in an arithmetic unit. The first data selector selects either the address from the address register or the data from the register file, and the second data selector selects either the data from the increment register or the destination field data included in each instruction. The decoder generates a signal to specify the data to be selected by the first and second data selectors. The adder receives data from the first and second selectors and provides an operand address. The third data selector receives the operand address from the adder and the address generated by the arithmetic unit, selects one of these addresses, and transfers the selected address to the address register.

High speed address calculation circuit for a pipeline-control-system

A request buffer apparatus controls a plurality of access requests to devices to be accessed (e.g., memory banks) commonly used by a plurality of accessing devices (e.g., a CPU, channels, and DMA units) in a data processing system. The apparatus has a request buffer means which has a plurality of buffers for storing the access requests. Write/read operations of the requests in and from the request buffer means are randomly performed in accordance with the status of the device to be accessed corresponding to the request stored in the buffer. Requests corresponding to the same device to be accessed are written in the empty buffers of the request buffer means in the order they are generated, and are read out from the request buffer means in the order that they are written. Each device to be accessed has a buffer write address generating means, and the buffer write status of each buffer is indicated so as to obtain the next buffer write address.

Buffer apparatus for controlling access requests among plural memories

An input/output start instruction includes, as parameters, a channel number, an input/output device number, a channel control block address and a termination que number. A channel receives the channel control block address and reads out the contents of the channel control block from a main memory and sets it in a service table in the channel whereby an input/output processing is executed.

Input/output control system and methods

Disclosed is a memory control system for a data processing system in which the length of an access unit to a memory can be different from the lengths of information words which can be processed and which can include data, addresses, and instructions and operands processed in an arithmetic control apparatus, and combinations thereof. The disclosed memory control system provides an address boundary for effecting a read/write operation with respect to the memory of information words having a half-word length and a full-word length. The half-word length information words can correspond to 2n times a minimum word length, n being a positive integer, and the access unit length can be equal to the minimum unit word length. In a disclosed embodiment, the minimum unit word length and the access unit length can be an 8 bit byte. Thus, a half-word length can be 16 bits and a full-word length can be 32 bits.

Memory control system

An information processing system having a main memory unit, an arithmetic control unit, and a plurality of input/output units, is comprised of a first bus, which is bidirectional, commonly connecting the main memory unit, the arithmetic control unit, and at least one input/output unit, a bus controller for controlling data transfer between two units connecting to the first bus, a second bus, which is also bidirectional, commonly connecting to the arithmetic control unit with at least another input/output unit, and a bus control means which is provided in the arithmetic control unit and controls data transfer between two units connecting to the second bus. The information processing system uses various units connecting to the first and second buses in time sharing and multiplexing mode.

Growing community of inventors

Tokyo, Japan

Keizo Aoyagi