Intel Corporation

Other

Keith Zawadzki

Pushkar Ranade

Mohammad Enamul Kabir

Babita Dhayal

Doug B Ingerly

Conor P Puls

Avyaya Jayanthinarasimham

Hannes Greve

Han Li

Mukund Bapna

Christopher P Auth

Christopher M Pelto

Shakul Tandon

Leif R Paulson

John Kevin Taylor

Embodiments described herein may be related to apparatuses, processes, and techniques for a barrier that surrounds one or more dies which are electrically coupled with one or more electrical connections on a wafer. The barrier may be a hermetic barrier that is formed on a wafer prior to singulation to prevent moisture intrusion from a side of the wafer that may compromise the one or more electrical connections. Other embodiments may be described and/or claimed.

Hermetic barrier surrounding a plurality of dies

Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Moisture hermetic guard ring for semiconductor on insulator devices

The present invention discloses a method including: providing a substrate; forming recessed regions adjacent to both sides of a gate on the substrate; performing an angled co-implant of a species in two steps with two different energies and two different doses into the recessed regions; forming Silicon-Germanium in the recessed regions; forming source/drain extensions adjacent to both sides of the gate with a dopant; and performing an anneal to activate the dopant.

Ultra-abrupt semiconductor junction profile

Methods and associated structures of forming a microelectronic device are described. Those methods may include plasma etching a portion of a source/drain region of a transistor, and then selectively wet etching the source drain region along a () plane to form at least one () region in the recessed source/drain region.

Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby

A CMOS device having dual-epi channels comprises a first epitaxial region formed on a substrate, a PMOS device formed on the first epitaxial region, a second epitaxial region formed on the substrate, wherein the second epitaxial region is formed from a different material than the first epitaxial region, an NMOS device formed on the second epitaxial region, and electrical contacts coupled to the PMOS and NMOS devices, wherein the electrical contacts are self-aligned.

CMOS device with dual-epi channels and self-aligned contacts

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Portland, OR, United States of America

Keith Zawadzki