Chiaro Networks Ltd

Foundry Networks, Inc.

Hewlett-packard Development Company, L.p.

Keith W Shaw

Tony M Brewer

Gregory S Palmer

Jim Kleiner

Harold Wallace Dozier

Thomas C McDermott, Iii

Harry C Blackmon

David Traylor

Bryan D Hornung

Dean E Walker

Paul F Vogel

Instead of alternatively utilizing only one fabric or the other fabric of a redundant pair, both fabrics simultaneously transmit duplicate information, such that each packet forwarding module (PFM) receives the output of both fabrics simultaneously. In real time, an internal optics module (IOM) analyzes each information chunk coming out of a working zero switch fabric; simultaneously examines a parallel output of a working one duplicate switch fabric; and compares on a chunk-by-chunk basis the validity of each and every chunk from both switch fabrics. The IOM does this by examining forward error correction (FEC) check symbols encapsulated into each chunk. FEC check symbols allow correcting a predetermined number of bit errors within a chunk. If the chunk cannot be corrected, then the IOM provides indication to all PFMs downstream that the chunk is defective. Under such conditions, the PFMs select a chunk from the non-defective switch fabric. Under error-free normal conditions, however, the PFMs select a chunk arbitrarily from a default switch fabric. In this way, each chunk in real time is selected from a non-defective source and is thus guaranteed to be error free. Accordingly, if a switch fabric fails, no information chunks are lost anywhere in the system.

Router switch fabric protection using forward error correction

In a multi-QOS level queuing structure, packet payload pointers are stored in multiple queues and packet payloads in a common memory pool. Algorithms control the drop probability of packets entering the queuing structure. Instantaneous drop probabilities are obtained by comparing measured instantaneous queue size with calculated minimum and maximum queue sizes. Non-utilized common memory space is allocated simultaneously to all queues. Time averaged drop probabilities follow a traditional Weighted Random Early Discard mechanism. Algorithms are adapted to a multi-level QOS structure, floating point format, and hardware implementation. Packet flow from a router egress queuing structure into a single egress port tributary is controlled by an arbitration algorithm using a rate metering mechanism. The queuing structure is replicated for each egress tributary in the router system.

System and method for router queue and congestion management

A centralized arbitration mechanism provides that a router switch fabric is configured in a consistent fashion. Remotely distributed packet forwarding modules determine which data chunks are ready to go through the optical switch and communicates this to the central arbiter. Each packet forwarding module has an ingress ASIC containing packet headers in roughly four thousand virtual output queues. Algorithms choose at most two chunk requests per chunk period to be sent to the arbiter, which queues up to roughly 24 requests per output port. Requests are sent through a Banyan network, which models the switch fabric and scales on the order of NlogN, where N is the number of router output ports. Therefore a crossbar switch function can be modeled up to the 320 output ports physically in the system, and yet have the central arbiter scale with the number of ports in a much less demanding way. An algorithm grants at most two requests per port in each chunk period and returns the grants to the ingress ASIC. Also for each chunk period the central arbiter communicates the corresponding switch configuration control information to the switch fabric.

System and method for router central arbitration

In a router with redundant central arbiters, a set of control processors (CPs) determines which arbiter is active, which is standby, and when to switch between them. In normal operation ingress ASICs issue requests to the active central arbiter ASIC and keep-alive requests cyclically once per chunk period to the passive arbiter ASIC, which then returns keep-alive grants through the same links to the ingress ASICs and sends standby configuration information to the optical switch ASICs. The arbiter ASICs pass a switch-over decision simultaneously to the optical switch ASICs and ingress ASICs, which empty all queues of outstanding requests, and then resend all of those requests to the new active central arbiter after all queues are empty, such that no router traffic is lost. Mechanisms ensure that during the transition the ASICs properly recognize which data links are healthy and which arbiter is active.

System and method for router arbiter protection switching

A system for performing data error recovery includes a memory unit and a memory controller. The memory unit includes a plurality of memory locations, and the memory controller maintains a checksum in one of the memory locations. At various times, the memory controller receives requests to update the checksum with data values identified by the requests. In response, the memory controller combines the checksum with these data values and stores the foregoing data values into memory. In one embodiment, the memory controller stores the foregoing data values into a plurality of stacks based on which protection domains are associated with the data values. In response to a detection of a data error, the memory controller retrieves a plurality of the stored data values and recovers a previous state of a particular memory location by combining each of the retrieved data values to the checksum.

System and method for performing backward error recovery in a computer

Router line cards are partitioned, separating packet forwarding from external or internal interfaces and enabling multiple line cards to access any set of external or internal data paths. Any failed working line card can be switchably replaced by another line card. In particular, a serial bus structure on the interface side interconnects any interface port within a protection group with a protect line card for that group. Incremental capacity allows the protect line card to perform packet forward functions. Logical mapping of line card addressing and identification provides locally managed protection switching of a line card that is transparent to other router line cards and to all peer routers. One-for-N protection ratios, where N is some integer greater than two, can be achieved economically, yet provide sufficient capacity with acceptable protection switch time under 100 milliseconds. Alternatively, protect line cards can routinely carry low priority traffic that is interruptible, allowing the protect line card to handle higher priority traffic previously carried by a failed working line card. This approach renders unnecessary engineering a network for less than full capacity to allow rerouting in the event of individual line card failure. Consequently, all data paths can be fully utilized. If a particular interface module on one data bus needs removal for maintenance, a duplicate data bus is available intact, allowing hot replacement of any working or protect interface module, even while a line card protection switch is in effect.

Router line card protection using one-for-N redundancy

A data storage system utilizes a plurality of memory systems, at least one processor, and a mapping system. Each of the memory systems has memory and a memory controller for storing and retrieving data. The processor transmits requests for writing data values. These requests include bus addresses. The mapping system maps the bus addresses into memory addresses. The mapping system maps consecutive bus addresses such that the memory addresses mapped from the consecutive bus addresses are interleaved across a plurality of the memory systems. In response to the foregoing requests from the processor, the mapping system identifies checksum system identifiers that identify locations where checksum values to be updated based on the aforementioned data values are stored. The checksum system identifiers preferably identify each of the plurality of mapping systems so that the checksum identifiers and, therefore, the checksum updates that occur based on these checksum system identifiers are interleaved across these memory systems.

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Plano, TX, United States of America

Keith W Shaw