Honeywell International Inc.

Honeywell G.m.b.h.

Keith W Golke

Paul S Fechner

David K Nelson

Harry H L Liu

Michael S Liu

Robert L Rabe

Gregor D Dougal

Thomas E Hendrickson

James Douglas Seefeldt

Eric E Vogt

Bradley J Larsen

Mai T MacLennan

Charles C Huang

Jeff Graebel

Theodore T Ta

Gregory D Dougal

Malt MacLennan

Harry Hl Liu

An apparatus for reading a bit of a memory array includes a bit cell column, voltage enhancement circuitry, and control circuitry. The voltage enhancement circuitry is configured to couple a bitline to a reference node. The control circuitry is configured to, in response to a read request for a bitcell element of a plurality of bitcell elements, couple a current source to the bitcell column such that a read current from the current source flows from the source line, through the bitcell column and the voltage enhancement circuitry, to the reference node and determine a state for the bitcell element based on a voltage between the source line and the reference node. The voltage enhancement circuitry is configured to generate, when the read current flows through the voltage enhancement circuitry, a voltage at the bitline that is greater than a voltage at the reference node.

Memory array with reduced leakage current

A configuration for a carbon nanotube (CNT) based memory device can include multiple CNT elements in order to increase memory cell yield by reducing the times when a memory cell gets stuck at a high state or a low state.

Memory cell with redundant carbon nanotube

A desired current through a carbon nano tube (CNT) element of a CNT memory device can be controlled by a wordline voltage, and a voltage on the CNT common node can be held constant. The common node can be constant at a source voltage if a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) is used in the CNT memory device, or the common node can be constant at a supply voltage if an n-channel MOSFET is used in the CNT memory device.

Carbon nanotube memory cell with enhanced current control

A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

Radiation-hardened memory element with multiple delay elements

This disclosure describes voting circuits where an output is generated based on a plurality of inputs. A first plurality of logic paths connects the output to a high voltage. Each logic path of the first plurality of logic paths includes two transistors. A second plurality of logic paths connects the output to the low voltage. Each logic path of the second plurality of logic paths comprises two transistors. Based on N or N&#x2212;1 of the inputs agreeing, the output is driven to either the low voltage or the high voltage via a subset of logic paths of the first and second plurality of logic paths.

(N-1)-out-of-N voter mux with enhanced drive

This disclosure is directed to techniques for preventing or reducing perturbations of an output signal of a differential amplifier caused by ionizing radiation incident upon the amplifier. The amplifier may include an amplification module that includes a plurality of amplification units configured to amplify a difference between a first component and a second component of a differential voltage signal to generate a plurality of amplified difference signals each corresponding to the amplified difference. The amplifier may further include a combination module that combines the plurality of amplified difference signals to generate a common output signal corresponding to the amplified difference.

Radiation hardened differential amplifier

The disclosure describes an antenna protection circuit for use in circuits where Single Event Transients from energetic particles is a concern. The antenna protection circuit may include at least three diodes, connected electrically in series and arranged such that at most all but one of the at least three diodes produce a transient current pulse from an energetic particle. During the transient current pulse event, the remaining diode remains reverse biased thereby sufficiently blocking the transient current pulse and an SET does not occur on the signal node. The antenna protection circuit may be constructed so that no unshorted parasitic p-n junction structure is associated with any of the diodes in the circuit, which would otherwise have to be explicitly included in the at least three diodes.

Non-aligned antenna effect protection circuit with single event transient hardness

A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.

Direct contact to area efficient body tie process flow

A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

SRAM split write control for a delay element

Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.

Simulating a dose rate event in a circuit design

A hardening system includes a data storage device having a data input, a clock input, a data node Q, and a data complement node QN. The data storage device provides drive to the data node Q and the data complement node QN. A hardening circuit includes first, second, third, fourth, and fifth transistor circuits. The first and second transistor circuits form a first node therebetween, and the first transistor circuit prevents the data node Q from changing states in the presence of radiation. The third and fourth transistor circuits form a second node therebetween, and the third transistor circuit prevents the data complement node QN from changing states in the presence of radiation. The first node is coupled to the third transistor circuit, and the second node is coupled to the first transistor circuit. The fifth transistor circuit prevents the first and second nodes from floating.

Full rail drive enhancement to differential SEU hardening circuit while loading data

A hardening circuit is provided for an integrated circuit which includes a data state reinforcing feedback path having a data node Q and a data complement node QN. A first hardening transistor is coupled between a rail and the data node Q, and a second hardening transistor coupled between the rail and the data complement node QN. The first and second hardening transistors provide additional drive to the data node Q and the data complement node QN. Gate controls operate the first and second hardening transistors and provide full rail drive to SEU sensitive nodes.

Full rail drive enhancement to differential SEU hardening circuit

A method for forming a frontside substrate contact on a Silicon-On-Insulator wafer in the presence of planarized contact dielectric is described. The method offers the improvement of reducing the etch selectivity requirements while allowing simultaneous etching and metallization of gate, source, drain and substrate contacts.

Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics

A multi-purpose device that can serve as either a resistor, MOSFET or JFET is disclosed. The resistor is formed by selecting a first metal interconnect configuration, the MOSFET is formed by selecting a second metal interconnect configuration, and the JFET is formed by selecting a third metal interconnect configuration. Because of the dual transistor/resistor nature of this device, the density of a typical gate array that uses resistors may be increased. In addition, and because no special processing is typically required, the device may be desirable for use in other types of structures such as standard cells and custom logic.

Integrated circuit impedance device and method of manufacture therefor

A SEU hardening circuit for use with a data storage circuit is described. The SEU hardening circuit may use a transmission gate to provide full rail drive during a write operation. The SEU hardening circuit may also be configured so that the transistors of the SEU hardening circuit are not susceptible to parasitic bipolar turn-on particularly during a radiation event, which can increase the SEU protection provided by the circuit.

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Minneapolis, MN, United States of America

Keith W Golke