International Business Machines Corporation

Ebara Corporation

Keith Thomas Kwietniak

Hariklia Deligianni

Panayotis Constantinou Andricacos

Wilma Jean Horkans

Soon-Cheon Seo

Peter Stevens Locke

Chih-Chao Yang

Lawrence Alfred Clevenger

Yun-Yu Wang

Stephen Edward Greco

Kwong Hon Wong

Sung Kwon Kang

Mizuki Nagai

Hiroyuki Kanda

Madhav Datta

Satoru Yamamoto

Erick G Walton

James Edward Fluegel

Keiichi Kurashina

Philippe Mark Vereecken

Dean S Chung

Cyprian Emeka Uzoh

John Ulrich Knickerbocker

Sampath Purushothaman

Timothy Joseph Dalton

Kenneth Parker Rodbell

Sandra Guy Malhotra

Andrew Herbert Simon

John Michael Cotte

Conal Eugene Murray

Koji Mishima

Emanuel Israel Cooper

Fenton Read McFeely

Leathen Shi

Ho-Ming Tong

Michael Wayne Lane

Darryl D Restaino

Christopher Carr Parks

Gangadhara Swami Mathad

Cornelia Kang-I Tsang

Michelle Leigh Steen

Hidenao Suzuki

Daniel Guidotti

Ryoichi Kimizuka

Steven H Boettcher

Brett Caroline Baker-O'Neal

Veeraraghaven S Basker

Brett Baker

Phillipe Vereecken

W Jean Horkans

Methods are provided for fabricating silicon carriers with conductive through-vias that allow high-yield manufacture of silicon carrier with low defect density. In particular, methods are provided which enable fabrication of silicon carries with via diameters such as 1 to 10 microns in diameter for a vertical thickness of less than 10 micrometers to greater than 300 micrometers, which are capable robust to thermal-mechanical stresses during production to significantly minimize the thermal mechanical movement at the via sidewall interface between the silicon, insulator, liner and conductor materials.

Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density

An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

Void-free damascene copper deposition process and means of monitoring thereof

A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

Plating apparatus and plating method

A plating method is capable of preferentially precipitating a plated film fully and uniformly in trenches and via holes according to a mechanical and electrochemical process, and of easily forming a plated film having higher flatness surface without being affected by variations in the shape of trenches and via holes. The plating method includes a first plating process and a second plating process. The second plating process is performed by filling a plating solution between an anode and a substrate, with a porous member placed in the plating solution, repeatedly bringing the porous member and the substrate into and out of contact with each other, passing a current between the anode and the substrate while the porous member is being held in contact with the substrate.

Plating method and plating apparatus

Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &#x3bc;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.

Electroplated copper interconnection structure, process for making and electroplating bath

The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

Method to generate porous organic dielectric

Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.

Deep filled vias

A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

Method for electroplating on resistive substrates

Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.

Method of controlling additives in copper plating baths

A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.

Method of improving contact reliability for electroplating

An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

Flip-Chip interconnections using lead-free solders

The present invention provides a means of fabricating a reliable C4 flip-chip structure for low-temperature joining. The electrochemically fabricated C4 interconnection has a barrier layer between the electroplated tin-rich solder bump and the ball-limiting metallurgy that protects the terminal metal in the ball-limiting metallurgy from attack by the Sn in the solder. The barrier layer is electroplated through the same photoresist mask as the solder and thus does not require a separate patterning step. A thin layer of electroplated nickel serves as a reliable barrier layer between a copper-based ball-limiting metallurgy and a tin-lead (Sn--Pb) eutectic C4 ball.

Barrier layers for electroplated SnPb eutectic solder joints

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Highland Falls, NY, United States of America

Keith Thomas Kwietniak