Advanced Risc Machines Limited

Keith S Clarke

A data processing system is provided in which the central processing unit clock signal (mclk, fclk) to a central processing unit core (14) may be suspended to reduce power consumption. This suspension is controlled by a suspend controller (20) that responds to a write request to a predetermined address (0x0320001C) to hold asserted a bus request signal (REQ) that cooperates with a bus controller (18) to block the central processing unit clock signal. The central processing unit core sees the suspend mode as a write request of an indefinite length. The suspend controller is responsive to an asynchronous input signal (FIQ, IRQ, EVENT1) to exit the suspend mode by issuing a bus acknowledge signal (ACK) and removing the block on the central processing unit clock signal.

Controlling processing clock signals

A data processing system having a first circuit and a second circuit that together control a third circuit by a respective first control signal and a second control signal. The first circuit issues a request signal to the second circuit to trigger initiation of the operation of the third circuit and the second circuit returns a grant signal to the first circuit to indicate that operation of the third circuit has completed. An advance controller within the second circuit serves to start to synchronize the grant signal back to the clock signal of the first circuit at one of a plurality of possible times that is selected to match the relative frequencies of the clock signals driving the first circuit and the second circuit.

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Cambridge, United Kingdom

Keith S Clarke