Texas Instruments Corporation

Keith Ryan Green

Dok Won Lee

William David French

Rajni J Aggarwal

Ajit Sharma

Borna J Obradovic

Jo Bito

Iouri N Mirgorodski

Byron Jon Roderick Shulver

Ricky A Jackson

Dimitar Trifonov

Tony Ray Larson

Scott Robert Summerfelt

Benjamin Stassen Cook

Marie Denison

Erika Lynn Mazotti

Charles Parkhurst

Anuj Jain

Michael Edwin Butenhoff

Anthony Gene Antonacci

Gabriel Eugenio De La Cruz Hernandez

Yong Liu

Yizhong Xie

Paul Ehnis

Chao-Hsuian Tsay

A Hall effect sensor including a Hall element disposed at a surface of a semiconductor body, including a first doped region of a first conductivity type disposed over and abutted by an isolated second doped region of a second conductivity type. First through fourth terminals of the Hall element are in electrical contact with the first doped region, and a fifth terminal in electrical contact with the second doped region. A Hall effect sensor includes a first current source coupled to the first terminal of the Hall element, and common mode feedback regulation circuitry. The common mode feedback regulation circuitry has an output coupled to the third terminal and a ground node, and having an input coupled to the second and fourth terminals of the Hall element, and an output coupled to the third terminal and a ground node, where the second doped region is coupled to the third terminal.

Hall effect sensor with reduced JFET effect

In one example, circuitry is formed in a semiconductor die. A magnetic concentrator is formed on a surface of the semiconductor die and over the circuitry. An isolation spacer is placed on a lead frame. The semiconductor die is placed on the isolation spacer, and the magnetic concentrator is aligned to overlap the lead frame. Electrical interconnects are formed between the semiconductor die and the lead frame.

Integrated current sensor with magnetic flux concentrators

An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.

Silicon hall sensor with low offset and drift compensation coils

A microelectronic device has a Hall sensor that includes a Hall plate in a semiconductor material. The Hall sensor includes contact regions in the semiconductor material, contacting the Hall plate. The Hall sensor includes an isolation structure with a dielectric material contacting the semiconductor material, on at least two opposite sides of each of the contact regions. The isolation structure is laterally separated from the contact regions by gaps. The Hall sensor further includes a conductive spacer over the gaps, the conductive spacer being separated from the semiconductor material by an insulating layer.

Hall sensor with dielectric isolation and p-n junction isolation

A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.

Hall sensor with performance control

A packaged current sensor includes a lead frame, an integrated circuit, an isolation spacer, a first magnetic concentrator, and a second magnetic concentrator. The lead frame includes a conductor. The isolation spacer is between the lead frame and the integrated circuit. The first magnetic concentrator is aligned with the conductor. The second magnetic concentrator is aligned with the conductor.

A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.

Hall-effect sensor with reduced offset voltage

A structure includes a substrate which includes a surface. The structure also includes a horizontal-type Hall sensor positioned within the substrate and below the surface of the substrate. The structure further includes a patterned magnetic concentrator positioned above the surface of the substrate, and a protective overcoat layer positioned above the magnetic concentrator.

Magnetic flux concentrator for in-plane direction magnetic field concentration

A device having a first terminal region and a second terminal region. The first terminal region includes fine-tune (FT) metal stripes that are separated from each other by a first distance along the longitudinal direction. The second terminal region is spaced apart from the first terminal region by at least an inter-terminal distance. The second terminal region includes coarse-tune (CT) metal stripes that are separated from each other by a second distance along the longitudinal direction. The second distance is greater than the first distance, and the inter-terminal distance greater than the second distance. Each of the FT metal stripes may be selected as a first access location, and each of the CT metal stripes may be selected as a second access location. A pair of selected first and second access locations access a sheet resistance defined by a distance therebetween.

Thermistor with tunable resistance

A CMOS integrated circuit includes a Hall sensor having a Hall plate formed in a first isolation layer which is formed concurrently with a second isolation layer under a MOS transistor. A first shallow well with a conductivity type opposite from the first isolation layer is formed over, and extending to, the Hall plate. The first shallow well is formed concurrently with a second shallow well under the MOS transistor. The Hall sensor may be a horizontal Hall sensor for sensing magnetic fields oriented perpendicular to the top surface of the substrate of the integrated circuit, or may be a vertical Hall sensor for sensing magnetic fields oriented parallel to the top surface of the substrate of the integrated circuit.

Hall sensor with buried hall plate

A Hall effect sensor comprises a semiconductor substrate, a first well formed in the semiconductor substrate, a first ohmic contact formed in the first well, a second ohmic contact formed in the first well, a first terminal electrically coupled to the first ohmic contact, a second terminal electrically coupled to the second ohmic contact, and a first metal layer formed over the semiconductor substrate. The first metal layer comprises a first interconnect and a first trace, where the first trace is formed over the first well, and where the first interconnect electrically couples a first part of the first well to a second part of the first well. The first and second ohmic contacts are each positioned between the first part and the second part of the first well, where the first interconnect is electrically isolated from the first trace.

Hall effect sensors with a metal layer comprising an interconnect and a trace

A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.

Well-based vertical Hall element with enhanced magnetic sensitivity

A microelectronic device includes a vertical Hall sensor for measuring magnetic fields in two dimensions. In one implementation, the disclosed microelectronic device involves a vertical Hall plate with a cross-shaped upper terminal and a lower terminal which includes a buried layer. The cross-shaped upper terminal has a length-to-width ratio of 5 to 12 where it contacts the vertical Hall plate. The length is measured from one end of one arm of the cross-shaped upper terminal to an opposite end of an opposite arm. The width is an average width of both arms. Hall sense taps are located outside of the cross-shaped upper terminal. Current returns connect to the buried layer.

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Prosper, TX, United States of America

Keith Ryan Green