Logic Devices Incorporated

Star Semiconductor Corporation

Keith Rouse

Jeffrey I Robinson

Terry F Montlick

Andrew J Krassowski

Bruce R Musicus

An apparatus architecture is provided which permits an easily programmed apparatus (,) to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus (,) is connected to a communications bus (,) which receives apparatus parameter, topological, and microinstruction information from a host processor and/or memory (EPROM). The apparatus includes numerous functional blocks (,), a core (,), and a parametric/microinstruction bus (,). The functional blocks include serial (,) and parallel ports (,), D/A (,) and A/D (,) converters, and programmable signal processors (,) which serve to process signal data and are connected in any desired manner through a switching matrix (,) located in the core. The topology of the switching matrix (,) is received via the communications bus (,). Parameters and microinstructions for the programmable signal processors (,) are sent via the communications bus (,), the core (,), and the parametric/microinstruction (,) bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports (,) and via the D/A and A/D (,) converters of the apparatus. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the apparatus.

Programmable digital signal processor integrated circuit device and method for designing custom circuits from same

A programmable integrated signal processor ('SPROC') is provided having a multiported central memory unit (RAM), a program memory, at least one, and preferably a plurality of digital processors coupled to the multiported RAM and to the program memory, a data flow manager which controls external data flowing into the SPROC and processed data flowing out of the SPROC by acting as an interface of such data with the multiported RAM, input and output ports coupled to the DFM and acting as serial interfaces for the SPROC, and a host port permitting the programming of the SPROC and acting as a parallel interface to the SPROC. SPROCs may be coupled via the input and output ports to provide a system. The SPROC architecture permits the SPROC system to be computationally expandable, to have low latency and parasitic overhead for real time I/O, to efficiently execute a multiple of asynchronous processes, and to easily interface with microprocessors of various formats. The SPROC architecture in conjunction with a compiler and user interface system permits a user to 'sketch and realize' complex circuits in the SPROC. An access port coupled to the multiported data RAM and the program RAM is provided for debugging purposes and permits reading and writing to data and program RAM memory locations. A probe permits monitoring of a memory location and provides an analog signal indicative thereof. The SPROC accomplishes for signal processing that which a microprocessor accomplishes for logic processing, and is further also easily realized in silicon.

Real time programmable signal processor architecture

Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) and tasks for a decision-making microprocessor. The SPROC is provided with a non-interrupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user's design. In automatically implementing the block diagram into silicon, the SPROC programming/development environment accounts for and provides software connection and interfaces with a host microprocessor. The programming environment preferably includes: a high-level computer screen entry system which permits choosing, entry, parameterization, and connection of a plurality of functional blocks; a functional block cell library which provides source code representing the functional blocks; and a signal processor scheduler/compiler which uses the functional block cell library and the information entered into the high-level entry system to compile a program and to output source program code for a program memory and source data code for the data memory of the (SPROC), as well as a symbol table which provides a memory map which maps SPROC addresses to variable names which the microprocessor will refer to in separately compiling its program.

System for dividing processing tasks into signal processor and

An event signalling system is provided for a digital signal processor apparatus which has a central data RAM, at least one computing processor, each computing processor having event occurrence circuitry, a plurality of data I/O processors, and a data RAM bus coupled to the data RAM, the computing processor(s) and the I/O processors. The event signalling system includes an address code generating circuit in each data I/O processor for generating different predetermined address codes for each I/O processor and for writing the predetermined address codes onto the data RAM bus upon the occurrence of events of interest. The occurrence of the predetermined address codes on the data RAM bus. are monitored by an address decoder which generates different signals depending upon the predetermined address code found. The signals from the address decoder are carried by a flag bus to the event occurrence circuitry of the computing processor(s), and to the output sections of the I/O processors.

Event signalling system and method for processor system having central

Architectures and methods for dividing processing tasks into tasks for a

A real time probe device is provided for a digital signal processor having a multiported data RAM, a time division multiplexed data RAM bus, and a processor. The probe includes a programmable comparator coupled to the address lines of the data RAM bus for determining that data is being written to a location of the multiported data RAM specified by the programmable comparator, a circuit for receiving the data on the data lines of the data RAM bus and for writing the data to a data buffer in the multiported data RAM, a reading circuit for obtaining the data from the data buffer of the multiported data RAM, and preferably a digital to analog converter for receiving at regular intervals the data obtained from the multiported data RAM and providing an analog signal therefrom. The average data rate at which data is written to the buffer in the data RAM should be the same as the rate at which data is obtained from the buffer of the data RAM for D/A conversion. Preferably, the buffer of the multiported data RAM into which the data is written and read by the probe is of variable length depending upon the RAM address to be probed. In this manner, delay is kept to a minimum.

Growing community of inventors

Oxford, CT, United States of America

Keith Rouse