Intel Corporation

Qualcomm Incorporated

Google Inc.

Keith Robert Pflederer

Vedaraman Geetha

Dean A Mulla

Amit Kumar

Ramkumar Srinivasan

Vikas Kumar Sinha

Rahul Jagdish Thakur

Jason Rupert Redgrave

Manu Gulati

Albert Meixner

Kai Cheng

Bahaa Fahim

Benjamin K Dodge

Allan Douglas Knies

Meenakshisundaram Chinthamani

Vinod Chamarty

Xiaoyu Ma

Malcolm Mandviwalla

Hongil Yoon

Weiping Liao

Mohan J Kumar

Rahul Khanna

James B Crossland

Sameer Nanda

Shivnandan D Kaushik

Ashish Gupta

Lily Pao Looi

Vyacheslav Vladimirovich Malyugin

Luigi Semenzato

Santhosh Rao

Aaron Durbin

Hsiao-Heng Kelin Lee

Stanley Steven Kulick

System memory address decoding for interleaving addresses across physical regions of a system on hip (SOC) and across shared memory resources in a processor based system and related hashing circuits are disclosed. In exemplary aspects, the SoC is configured to discover, for every range of addresses, the number of physical regions and the number and/or size of the shared memory resources available including caches, snoop filters and memory interfaces within each physical region. The SoC may include a system memory address decoding circuit that is configured to adaptively decode a memory address based on the memory address range in which the system address resides and then direct such memory access request to the proper shared memory resource so that each address in the memory address range spans across all of the shared memory resource in the range.

System memory address decoding for interleaving addresses across physical regions of a system-on-chip (SOC) and across shared memory resources in a processor-based system

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Methods and systems for memory bandwidth control

Resources of an electronic device are partitioned into a plurality of resource portions to be utilized by a plurality of clients. Each resource portion is assigned to a respective client, has a respective partition identifier (ID), and corresponds to a plurality of memory bandwidth usage states tracked for a plurality of memory blocks. For each resource portion, each of the memory bandwidth usage states is associated with a respective memory block and indicates at least how much of a memory access bandwidth assigned to the respective partition ID to access the respective memory block is used. A usage level is determined for each resource partition based on the memory bandwidth usage states, and applied to adjust a credit count. When the credit count is adjusted beyond a request issue threshold, a next data access request is issued from a memory access request queue for the respective partition ID.

Innovative techniques to efficient stripe ordered writes across multiple socket-to-socket links. The ordered writes may be PCIe ordered writes. Each socket-to-socket write (or remote write) for an address may be converted into two transactions. The first transaction may ensure that coherency for the address is ensured. The second transaction may be the actual request transaction to write the data of the address. In so doing, when multiple remote writes are involved, the remote writes may be distributed over multiple socket-to-socket links to maximize bandwidth.

Efficiently striping ordered PCIe writes across multiple socket-to-socket links

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Way partitioning for a system-level cache

Systems, devices, and methods for managing fragmentation in hardware-assisted compression of data in physical computer memory which may result in reduced internal fragmentation. An example computer-implemented method comprises: providing, by a memory management program to compression hardware, a compression command including an address in physical computer memory of data to be compressed and a list of at least two available buffers for storing compressed data; using, by the compression hardware, the address included in the compression command to retrieve uncompressed data; compressing the uncompressed data; and selecting, by the compression hardware, from the list of at least two available buffers, at least two buffers for storing compressed data based on an amount of space that would remain if the compressed data were stored in the at least two buffers, wherein each of the at least two selected buffers differs in size from at least one other of the selected buffers.

Managing memory fragmentation in hardware-assisted data compression

Disclosed is an integrated circuit having a decompression block. The decompression block is configured as a pipeline that may include a length module and a distance module. The length module evaluates a length for each symbol. The distance module may resolve distances in an at least one length-distance pair. The length module may include a shifter stage configured to store two consecutive words, and control a sliding window of symbols, in order to extract literals or distances. The length module may include a mapper stage configured to map the literals or distances to positions in the output stream. The distance module may include a pointer replacement stage and a resolution stage. The pointer replacement stage configured to replace distances, represented as pointers within an output word, with either literals or other pointers to prior words. The resolution stage configured to replace the other pointers with literals, and output the literals.

ASIC block for high bandwidth LZ77 decompression

Embodiments of the invention are generally directed to apparatuses, methods, and systems for a computing system feature activation mechanism. In an embodiment, a computing system receives a remotely generated feature activation information. The computing system compares the remotely generated feature activation information with a built-in feature activation mechanism. In an embodiment, a feature of the computing system is activated if the remotely generated feature activation information matches the built-in feature activation mechanism. Other embodiments are described and claimed.

Computing system feature activation mechanism

In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in an affinity corresponding to the cache.

Line swapping scheme to reduce back invalidations in a snoop filter

In an embodiment, a method is provided. The method of this embodiment provides receiving a request for data from a processor of a plurality of processors, determining a cache entry location based, at least in part, on the request, storing the data in a cache corresponding to the processor at the cache entry location, and storing a coherency record corresponding to the data in a snoop filter in accordance with one of the following, if there is a cache miss: at the cache entry location of a corresponding affinity in the snoop filter if the cache entry location is found in the corresponding affinity, or at a derived cache entry location of the corresponding affinity if the cache entry location is not found in the corresponding affinity.

Partial way hint line replacement algorithm for a snoop filter

In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

Apparatus, system, and method to enable transparent memory hot plug/remove

A control hub includes a first interface and a second interface to transfer data. The first interface connects to a first bus. The second interface connects to a peripheral bus. The control hub receives configuration address and configuration data during a configuration access. The control hub transfers the configuration data between the first interface and the second interface without transferring the configuration data to a configuration data register. The control hub further includes other interfaces to allow access to peripheral devices for system management and testing purposes.

Growing community of inventors

San Jose, CA, United States of America

Keith Robert Pflederer