Infineon Technologies Ag

Intel Mobile Communications Gmbh

Morphics Technology, Inc.

Intel Deutschland Gmbh

Keith Rieken

Joel D Medlock

David Morris Holmes

Christopher Woodthorpe

Venugopal Balasubramonian

Paul Chou

Song Chen

Ravi Subramanian

Uma Jha

Chakki Kavoori

Murali Krishnan

David M Holmes

A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

Distributed micro instruction set processor architecture for high-efficiency signal processing

A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.

Distributed micro instructions set processor architecture for high-efficiency signal processing

A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.

Method and apparatus for time-sliced and multi-threaded data processing in a communication system

A method for processing data in a spread spectrum system, including decimating a data rate of received spread spectrum data by a decimation factor to a decimated rate; storing the received spread spectrum data into a memory at the decimated rate; interpolating the decimated rate by an interpolation factor to an interpolated rate; and reading the received spread spectrum data from the memory at the interpolated rate.

Method for processing data in a spread spectrum system

An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes several steps. The first step locates a memory address in the computer readable memory that is associated with a first hardware resource. In the next step, control information associated with the first memory address is transmitted to the first hardware resource for it to be operated. In the last step, a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource, is read.

Method and apparatus for software-based allocation and scheduling of hardware resources in a wireless communication device

An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.

Apparatus and methods for sample selection and reuse of rake fingers in spread spectrum systems

This invention provides a configurable multi-dwell search engine for performing automated efficient searches of a known code sequence space. Inputs from a multi-dwell table and a finger control table are multiplexed by a first multiplexer. Output from the first multiplexer is used to generate a threshold comparison signal. The generated threshold comparison signal, the current dwell state signal and inputs from a next dwell look-up table are multiplexed by a second multiplexer. The second multiplexer outputs a hard hit signal and a offset control signal.

Apparatus and method for configurable multi-dwell search engine for spread spectrum applications

An apparatus for digitally processing signals within wireless communications base-stations which includes a channel pooling signal processor and a digital signal processor. The channel pooling signal processor includes a plurality of computation units typically realized in a heterogeneous multiprocessing architecture, a test interface for testing the function of the plurality of the computation units, a general-purpose microprocessor for managing the dataflow into and out of the channel pooling signal processor as well as effecting the control and configuration of the computation units, and an interconnect mechanism for connecting the plurality of computation units to the input, output, test interface, and the general-purpose microprocessor.

Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks

A wireless communication system-on-a-chip comprises a system bus, a set of fixed function processors connected to the system bus, an embedded processor connected to the system bus, and reconfigurable logic connected to the system bus. The reconfigurable logic supports an operational mode and a diagnostic mode. In the operational mode, the system operates to support different air interface protocols and data rates. In the diagnostic mode, the system alternately tests the system, debugs the system, and monitors bus activity within the system.

Apparatus and method for implementing a wireless system-on-a-chip with a reprogrammable tester, debugger, and bus monitor

A rake receiver in accordance with an exemplary embodiment of this invention is configurable by an external agent (e.g., microcontroller, DSP, or state machine) to suit the particular requirements of different spread spectrum systems. In an exemplary embodiment, the receiver includes multiple fingers. Each finger includes a plurality of generic despreaders/descramblers, a plurality of generic dechannelizers coupled to the despreaders/descramblers, and at least one timing estimation controller coupled to the despreaders/descramblers. The finger also includes at least one phase estimation controller, at least one frequency estimation controller, and at least one energy estimation controller all coupled to the generic dechannelizers.

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Cupertino, CA, United States of America

Keith Rieken