Intel Corporation

Keith-Michael W Self

Shekhar Yeshwant Borkar

Stephen R Mooney

Edward Allyn Burton

James A Sutton, Ii

Linda J Rankin

George W Cox

Jerry G Jex

Craig B Peterson

Prantik K Nag

John A Urbanski

David W Archer

A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies. A second microprocessor may also be coupled to the first memory via a second point-to-point interface, the first microprocessor and the second microprocessor sharing the first memory for storage of information used by the first microprocessor and the second microprocessor. In this configuration, the first memory may include a duplicate cache store for the first microprocessor and the second microprocessor, in order to provide cache consistency for the two processors. The system may also include a first input-output device coupled via a second point-to-point interface to the first memory. A variety of topologies of processors, memories and input/output devices may be designed into 'clusters' wherein each cluster communicated with one another for accesses, remote and local, for accessing input/output devices, and for maintaining cache consistency.

Microprocessor point-to-point communication

A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver. A buffer accessing circuit is coupled to the buffer for referencing write locations to store the messages received from the transmitter over the communication bus, and for referencing read locations for reading the messages out of the buffer by the receiver. Finally, a delay locked loop circuit is coupled to the communication bus, the buffer accessing circuit and the buffer for providing the proper set-up and hold time requirements for the messages transmitted on the communication bus from the transmitter and storing the messages in the buffer.

Point-to-point phase-tolerant communication

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Aloha, OR, United States of America

Keith-Michael W Self