Intel Corporation

Keith M Self

Jeffrey E Smith

Jerry G Jex

Sanjay Dabral

Jed D Griffin

Charles E Dike

Timothy W Kelly

Brett A Prince

Stephen S Pawlowski

Keng L Wong

Matthew B Haycock

Ming Zeng

Craig B Peterson

John A Urbanski

Chaiyuth Chansungsan

Stephen W Kiss

Ernest Khaw

Michael Sandhinti

Chung-Wai Yue

Jim Sutton

Ramesh Senthinathan

Smith E Jeffrey

Robert Gatlin

In some embodiments, a transmitter includes first encoding controlled frequency output circuitry to creates a magnitude encoded controlled frequency signal (CFS) and second encoding controlled frequency output circuitry to create a complementary a magnitude encoded controlled frequency signal (CCFS). Other embodiments are described and claimed.

Controlled frequency signals

In some embodiments, a circuit includes a reference current source to provide a substantially noise free current signal, and a detector coupled to one or two power supplies. In some embodiments, a method includes receiving a substantially noise free current signal, receiving one or two power supply signals, processing the substantially noise free current signal and the one or two power supply signals to detect a noise signal in the one or two power supply signals, and generating a noise detection signal in response to detection of the noise signal.

Power supplies noise detector for integrated circuits

In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Receivers for controlled frequency signals

A bus has a first set of data lines and a second set of data lines. In an embodiment, the bus has a selector circuit to count the number of data lines in the first set of data lines and second set of data lines that have a certain value and to select one set of data lines to be inverted based on the count. In an embodiment, the bus has a first inverter to invert the set of data lines selected and a second inverter to re-invert the set of data lines selected at a receiver based on the value of an added control line.

Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect

An example embodiment of a computer system that includes a removable agent that can be removed or installed without powering down the system includes a fixed bus agent and the replaceable bus agent. The fixed bus agent and the replaceable bus agent are electrically coupled together by a presence detect signal, a synchronization signal, and a data bus. A deassertion of the presence detect signal indicates to the fixed bus agent that the removable bus agent has been disconnected and is no longer electrically coupled to the fixed bus agent. The fixed bus agent then tri-states its outputs and also prevents potentially invalid data from being delivered to the core circuitry of the fixed bus agent. An assertion of the presence detect signal indicates to the fixed bus agent that the replaceable bus agent is electrically connected to the fixed bus agent. In response to the assertion of the presence detect signal, the fixed bus agent and the replaceable bus agent enter reset periods. Following the reset periods and when each bus agent is ready to communicate to the other agent, the fixed bus agent and the replaceable bus agent signal to each other over the synchronization signal that each is ready to begin communication over the data bus.

Method and apparatus for removing and installing a computer system bus agent without powering down the computer system

A method and apparatus for detecting data strobe errors. A strobe error detection circuit has a strobe input and a counter coupled to the strobe input to count strobe pulses received. The circuit also has a comparator to determine if a strobe error has occurred based on the magnitude of the difference between a first count of strobe pulses and a second count of strobe pulses. In an embodiment, the first count is read from a memory location at a first time and the second count is read at a second time.

Method and apparatus for detecting strobe errors

An apparatus and method for debugging a bus including interposing a device that monitors the data transferred between two devices on the bus such that the bus is split into two busses, with data being copied for transmission to a diagnostics device as the data is transferred between the two busses.

Method and apparatus for debugging ternary and high speed busses

A method and apparatus is presented where for transmitting data between two or more components. Data signals are sent in parallel with a clocking signal (e.g., on a bus) so that the data signal can be latched in relation to the clocking signal. For example, two clocking signals, out of phase from each other by 180 degrees, can be sent on bidirectional clocking signal lines and data signals can be sent on a data signal line, the component receiving the clocking and data signals can latch the data signals on each high-to-low transition of either of the two clocking signals. Using the method and apparatus of the present invention, skew problems seen with other bus systems can be reduced which leads to an increase in data transfer rates.

Method and apparatus for source synchronous data transfer

An electronic circuit die is presented including a plurality of first and second input/output (I/O) pad buffer cells. The first I/O pad buffer cells include at least a latch for latching data signals received at a pad in the cell. Adjacent ones of these first I/O pad buffer cells are conductively coupled together using conductive trace pins. The second I/O pad buffer cells include a pad that receives clocking signal which are supplied to the latches of the first I/O pad buffer cells. Accordingly, data signals received at the pads of the die are latched in the pad as opposed to the core logic of the die. One benefit of providing the latching of data signals in the pad is that conductive traces between the latches and the core logic need not be precisely matched, thus reducing cost. Also, the first I/O pad buffer cells can be similarly constructed, thus reducing the complexity and cost of manufacture for the die.

Apparatus for receiving/transmitting signals in an input/output pad

Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity is described. In one embodiment the apparatus includes a first and a second integrated circuit wherein each integrated circuit includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL driver is coupled to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The first and second integrated circuits are cascade-coupled by coupling the first PLL driver of the first integrated circuit to the reference clock signal pin of the second integrated circuit using a propagation path of electrical length L3. In one embodiment a feedback path of electrical length L4 couples the first PLL driver and feedback pin of the first integrated circuit such that L3.apprxeq.L4. In one embodiment L1, L2, L3, and L4 have corresponding physical lengths D1, D2, D3, and D4, wherein D1.apprxeq.D2 and D3.apprxeq.D4. The cascaded integrated circuits enable providing synchronicity between components of a same tier as well as between multiple tiers of a hierarchical computer system architecture.

Cascaded multiple internal phase-locked loops for synchronization of

Methods and apparatus for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity at different frequencies is described. In one embodiment the apparatus includes a first phase-locked loop (PLL) formed on an integrated circuit die. A reference clock signal pin is coupled to the first PLL by a path of electrical length L1 for propagating a reference clock signal to the first PLL. A first PLL feedback pin is coupled to the first PLL by a path of electrical length L2, wherein L1.apprxeq.L2. The apparatus includes a programmable counter coupled to the reference clock signal pin, the programmable counter providing a divided reference clock signal to the first PLL. In one embodiment, the method includes the step of providing a reference clock signal to a plurality of PLLs residing within a same integrated circuit. The outputs of at least some of the PLLs are coupled to corresponding output pins of the integrated circuit. The following steps are performed for each selected output pin coupled to provide a synchronized clock signal at the end of a propagation trace: a) determining an electrical length of the propagation trace; and b) providing a feedback trace from the output pin to a feedback pin of the corresponding PLL, wherein the feedback trace is a same electrical length as the propagation trace. A divided-by-n reference clock signal is then provided to at least one of the PLLs, wherein n is not equal to 1.

Multiple internal phase-locked loops for synchronization of chipset

An apparatus and a method for easing design constraints with respect to placement of computer system components and subsystems requiring relative synchronicity are described. In one embodiment, the apparatus includes a first phase-locked loop (PLL) coupled to a reference clock pin by a path of length L1 and a first PLL feedback pin by a path of length L2 such that L1.apprxeq.L2. In another embodiment, the apparatus includes a second PLL coupled to the reference clock pin by a path of length L3. The second PLL is coupled to an internal core of the integrated circuit by a path of length L4 such that L3.apprxeq.L4. In one embodiment, a computer system incorporating the apparatus includes a first propagation path of length L5 coupled to the first PLL output pin. The first PLL output pin is coupled to the first PLL feedback pin by a path of length L6 such that L5.apprxeq.L6. The choice of electrical lengths allows relative synchronicity between the clock signals propagated to the internal core and the end of the first propagation path.

A fully asynchronous parallel synchronizer having staged write and read enables and an asynchronous interface for same. The asynchronous interface can be used to interconnect two processor systems (e.g., within a multiple processor system or a parallel processor system). The parallel programmable synchronizer contains n latches coupled in parallel having n individual enable lines having staggered enable signals. The latches are coupled such that they output to a multiplexing circuit that also receives individual staggered read enable signals which are based on the write enable signals. According to the parallel programmable synchronizer, data is written into a particular latch in clock cycle (i) just after other data was read from the same particular latch in a just prior clock cycle (i-1). While the synchronizer contains n latches, the number of latches used, x, for any particular embodiment is programmable and the enable signals adjust to accommodate the number of latches selected. The settling time for the synchronizer is therefore programmable while the synchronizer also provides a maximum throughput frequency (sampling rate). A novel empty flag generation is also described.

Fully asynchronous interface with programmable metastability settling

An asynchronous interface enabling a processor node operating at a first clocking frequency to transfer and receive information from a communications network operating at a second clocking frequency. The asynchronous interface comprises an input synchronizer and an output synchronizer. The input synchronizer asynchronously receives a first plurality of information packets from the processor node and synchronously transfers the first plurality of information packets into the communications network. The output synchronizer, however, synchronously receives a second plurality of information packets from the communications network and asynchronously transfers the second plurality of information packets into the processor node. Both the input and output synchronizers are coupled between the communications network and the processor node.

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Aloha, OR, United States of America

Keith M Self