International Business Machines Corporation

Keith M Selbo

Yogi K Puri

An FET driver circuit is disclosed which provides short circuit protection at the output node without reducing its performance. Grounded short circuit protection is achieved by sharing a load resistance at the output node in two parallel components, a low resistance active FET load and a high resistance active FET load. A delay element is inserted between the data input node and the gate for the low resistance active FET load. When the data input is low, both of the active FET load devices are off and the active logical FET device is on causing a low output value for the circuit. When the data input for the circuit goes high, the output capacitance is initially charged by the high resistance FET load device and is followed after a short delay, by charging through the low resistance FET load device. The low resistance FET load device cuts off current flow automatically after a predetermined period of time transpires. This delay duration is designed to be equal to or greater than the desired output rise time for the circuit, and less than the time required to destroy the low resistance device if it were to have its output terminal grounded. Thus, if the output of the circuit is accidentally shorted to ground, the circuit is protected because the brief on-time of the low resistance device limits power dissipation below destructive levels, and because the short circuit current in the high resistance device is of insufficient magnitude to cause problems.

Growing community of inventors

Manassas, VA, United States of America

Keith M Selbo