U.S. Philips Corporation

Keith M Hutchings

Andrew L Goodyear

Kenneth R Whight

Paul Arthur Gough

Andrew M Warwick

A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is former within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6). A fourth region (11) of the one conductivity type forms with a portion (6b) of the second region (6) of the opposite conductivity type remote from the recess (9) a further rectifying junction (12) which is reverse-biassed in at least one mode of operation of the device and has a predetermined breakdown voltage for causing the device to breakdown in the vicinity of the further rectifying junction (12) away from the recess (9) when a critical voltage is exceeded.

Semiconductor device having a vertical insulated gate field effect

A semiconductor device (1) includes a vertical insulated gate field effect device (2) and has a semiconductor body (3) with a first semiconductor region (4) of one conductivity type adjacent one major surface (5). A second semiconductor region (6) of the opposite conductivity type is formed within the first region (4) adjacent the surface (5) and a third region (7) forms with the second region (6) a rectifying junction (8) meeting the one major surface (5). A recess (9) extends into the first region (4) from the one major surface (5) so that the second and third regions (6 and 7) abut the recess (9), and an insulated gate (10) is formed within the recess (9) for controlling conduction between the first and third regions (4 and 7) along a conduction channel area (61) of the second region (6). A fourth region (11) of the one conductivity type forms with a portion (6b) of the second region (6) of the opposite conductivity type remote from the recess (9) a further rectifying junction (12) which is reverse-biassed in at least one mode of operation of the device and has a predetermined breakdown voltage for causing the device to breakdown in the vicinity of the further rectifying junction (12) away from the recess (9) when a critical voltage is exceeded.

Method of forming a semiconductor device having a vertical insulated

A semiconductor body (3) has a first region (4) of one conductivity type adjacent one major surface (5). A first masking layer (6) comprising at least one first mask window (6a) spaced from a second mask window (6b) is defined on the surface (5). Opposite conductivity type impurities are then introduced through the first masking layer (6) and a second masking layer (8) which is selectively removable with respect to the first masking layer (6) is subsequently provided on the first masking layer and patterned to leave a mask area (8a) covering the first mask window (6a). The semiconductor body (3) is then etched through the second mask window (6b) to define a recess (9) extending into the first region (4) while leaving the introduced impurities beneath the masked first mask window (6a) to form a relatively highly doped second region (7). The first and second masking layers (6 and 8) are removed and an insulated gate structure (10) is provided by defining a gate insulating layer (10a) on the recess walls (9a) and providing a gate conductive region (10b) on the insulating layer (10a). A relatively lowly doped third region (11) of the opposite conductivity type is provided to extend between the relatively highly doped second region (7) and the recess (9) to provide a conduction channel area (11a) adjacent the insulated gate structure (10). A fourth region (12) is provided to form a potential barrier (12a) with the relatively lowly doped third region (11) so that the conduction channel area (11a) provides a conductive path between the fourth and first regions (12 and 4).

Method of manufacturing a semiconductor device comprising an insulated

A mask (4) defining at least one window (4a) is provided on one major surface (1a) of a semiconductor body (1). The semiconductor body (1) is etched to define a groove (5) into a first region (2) of one conductivity type through a second region (3) of the opposite conductivity type. A relatively thin layer of gate insulator (6) is provided on the surface (5a) of the groove (5). A gate conductive region (7) of an oxidizable conductive material is provided within the groove (5) to define with the gate insulator layer an insulated gate structure (8) bounded by a conduction channel-defining area (30) of the second region (3). A step (15) in the surface structure is then defined by causing the insulated gate structure (8) to extend beyond the surrounding surface by oxidizing the exposed (7a) gate conductive material to define an insulating capping region (9) on the gate conductive region (3). A layer (10) is formed over the surface structure and etched anisotropically to leave portions (10a) of the layer on the side wall (8'a) of the step (15) defined by the insulated gate structure (8) and to define beneath the portions (10a) third regions (11) of the one conductivity type within the second region (3). An electrically conductive layer (12) is deposited to contact both the second and the third regions (3 and 11).

A semiconductor component (1a) has first and second insulated gate field effect devices (T1 and T2) formed within the same seminconductor body (2). The devices (T1 and T2) have a common first main electrode (D) and an arrangement (20) provides a resistive connection (20b) between a second main electrode (S2)of the second device (T2) and the insulated gate (G1) of the first device (T1). The second device (T2) is formed so as to be more susceptible than the first device (T1) to parasitic bipolar transistor action for causing, when the first and second devices (T1 and T2) are turned off and a voltage exceeding a critical voltage (V.sub.c) is applied to the common first main electrode (D), the parasitic bipolar transistor (B) within the second device (T2) to turn on producing a current for causing, by virtue of the resistive connection (20b) between the second main electrode (S2) of the second device (T2) and the insulated gate (G1) of the first device (T1), the voltage at the insulated gage (G1) of the first device (T1) to alter to cause the device (T1) to turn on. This allows the energy of the overvoltage to be dissipated by conduction of the first insulated gate field effect device to avoid any potentially damaging effects, such as irreversible bipolar breakdown or performance degradation due to hot carrier injection into the gate oxide.

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Groombridge, United Kingdom

Keith M Hutchings