Broadcom Corporation

Keith LaRell Klingler

Brian Francis Schoner

Darren Duane Neuman

Kevin Lee Miller

Sang Van Tran

Steven T Jaffe

Rajesh Mamidwar

Chengfuh Jeffrey Tang

Greg Alan Kranawetter

Patrick Y Law

Iue-Shuenn Chen

Sandeep Bhatia

Aleksandr M Movshovich

Jason C Demas

Francis Cheung

Brad Albert Delanghe

David A Baer

Hoang Nhu

Ut Nguyen

Tracy C Denk

Shawn Val Johnson

James Douglas Sweet

Yao-Hua Tseng

Jeffrey S Bauch

Guang-Ting Shih

Glen A Grover

David Chao Hua Wu

Brad Grossman

Chuck Monahan

Dan Simon

Thu T Nguyen

Hsien-Chih Jim Tseng

Ben Giese

Lakshman Ramakrishnan

Cam Minh Luu

Jeff Tingley

David Chaohua Wu

Benjamin S Giese

Shu Chan

Certain aspects of a method and system for a flexible multiplexer and mixer (FMM) are disclosed. Aspects of one method may include mixing primary audio information and secondary audio information of sampled received audio data based on corresponding metadata information to generate mixed output audio data. The generated mixed output audio data may be pulled through a plurality of pipeline stages.

Method and system for a flexible multiplexer and mixer

A television on a chip (TVOC) system that provides a cost effective approach for providing television functionality on a single integrated circuit chip is disclosed. A TVOC includes the functionality necessary to receive and display television signals in a variety of input and output formats. A TVOC can be used in set-top boxes for cable and satellite television, or directly within a television. All functionality provided can be provided on a single integrated circuit. TVOC includes a data transport module, an IF demodulator, a digital audio engine, an analog audio engine, a digital video engine, and an analog video engine. The TVOC also includes three sets of interfaces including output interfaces, control interfaces and ancillary interfaces. Further features and embodiments provide enhanced functionality and increased efficiencies.

Television functionality on a chip

A system and method for flexibly outputting audio from a plurality of programs to the particular outputs that are desired for each audio stream. This routing flexibility enables the audio system to operate in a variety of configured usage modes, wherein each usage mode identifies the routing of each audio stream to one or more outputs such as SPDIF, HDMI, I2S, and DAC.

Flexible multichannel outputs for dual audio decode

Certain aspects of a multi-channel signal synchronizer may comprise receiving a plurality of clock signals from a plurality of clock signal sources, wherein a portion of the received plurality of clock signals may be out of synchronization with a remaining portion of the received plurality of clock signals. A plurality of data signals may be received from a plurality of data signal sources, wherein a portion of the received plurality of data signals may be out of synchronization with a remaining portion of the received plurality of data signals. The received portion of plurality of clock signals and data signals may be synchronized to the received remaining portion of plurality of clock signals and data signals utilizing bit alignment and sample alignment. A plurality of synchronized output signals may be generated based on the synchronized received plurality of clock signals and synchronized received plurality of data signals.

Method and system for a multi-channel signal synchronizer

Provided is a system and method for communicating audio. A method includes transmitting audio information segments on a first signal line, each segment including a format portion representative of audio format modes, and a data portion having audio data corresponding to one or more of the format modes. The method also includes transmitting a number of synchronization markers on a second signal line. Each marker is representative of a timing of one of the audio information segments.

Method and system for a multi-channel audio interconnect bus

A system and method of verifying the format of a simulated signal produced during the simulation of an electronic circuit is disclosed. One aspect of the present invention includes a method of extracting timing information from a single simulated serial digital audio signal that comprises both data and clock. An embodiment of the present invention may verify operation of the simulated electronic circuit by setting the value of a first simulated signal according to predetermined events that occur in a second simulated signal. The second simulated signal may be parsed using timing information extracted from the second simulated signal, and the format of the second simulated signal may be matched against a predetermined format based upon the results of the parsing. An embodiment of the present invention may, for example, be employed during software simulation to verify the operation of exemplary devices such as application specific circuits (ASICs) used in the generation of signals meeting the Sony/Philips Digital Interconnect Format (SPDIF).

Flexible SPDIF verification tool

Provided is a system and method for muting zero level pulse code modulated (PCM) samples. PCM samples are received as inputs to a digital to analog converter (DAC) including a PCM input module and a mapping module. The method includes monitoring a level of the PCM samples received as inputs to the PCM input module and sensing consecutive zero level PCM samples from among the monitored input PCM samples. The method also includes muting a PCM input to the mapper when a predetermined number of zero level PCM samples have been sensed.

Method and system for providing zero detect and auto-mute

Provided is a system and method for converting digital data audio data audio data that has a predetermined input sample rate, into an analog data signal. A system includes a digital to analog converter (DAC) including a digital processing portion configured to receive as an input the digital audio data and timing information, the timing information being representative of a time base of the input sample rate. The digital processing portion is similarly configured to digitally process the digital audio data and the timing information to produce serialized output data. The DAC also includes an analog processing portion configured to convert serialized data to an analog format. The digital processing portion operates in accordance with at least one clock having a corresponding clock rate wherein the corresponding clock rate is unrelated to the input sample rate.

Method and system for converting digital samples to an analog signal

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San Diego, CA, United States of America

Keith LaRell Klingler