Bull Hn Information Systems, Inc.

Keith L Petry

James W Keeley

Thomas S Hirsch

Richard A Lemay

Chester M Nibby, Jr

A processing unit couples to a system bus and includes a microprocessor which tightly couples to a local memory. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which couples to the microprocessor and to the system bus. The EEPROM unit stores in first and second separate regions, on-board diagnostic (OBD) routines and boot routines, respectively. The OBD routines are organized into a plurality of categories or phases. The processing unit includes a register accessible only by the microprocessor which, under the control of the OBD routines, is loaded with a number of predetermined values at the beginning of each individual OBD routine for identifying a particular phase and subphase of testing to be performed. Means coupled to the register is directly connected to display a first phase portion of the contents of the register for indicating during which phase of testing a failure occurred. The phase and subphase contents of the register are used to identify the actual test which failed. This information provides an index into a test dictionary which indicates the specific component or group of components which failed.

On-board diagnostic testing

A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus. Following loading of the peer processor operating system, the EEPROM control circuits, in response to commands from the system bus, enable the microprocessor to address the second region for executing boot routines for loading its operating system.

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North Reading, MA, United States of America

Keith L Petry