Texas Instruments Corporation

Telogy Networks, Inc.

Keith Krasnansky

Zoran Mladenovic

William A Mills

Ronald S Drafz

A method for reducing soft error rates in semiconductor memory. In one embodiment, memory is partitioned into a) boot and download memory, b) program memory and c) data memory. Each partition receives protection according to the importance of the data stored. The boot memory is protected by sensing errors and repairing them utilizing on-chip data storage redundancy and exchange. The program memory is protected by sensing errors and repairing damaged data by reloading it using the program stored in the boot and download memory. The data memory is selectively protected similar to the program memory, but with the added feature of regular saving to disk from which to check for accurate data in the event of corruption. In another embodiment, any or all of the soft error protection features are selectable on a global basis, a memory type basis or, in the cases of program and data memory, on a block level basis.

Method to reduce soft error rate in semiconductor memory

A method of power consumption reduction in integrated circuits comprising extensive use of differential signaling within said circuits. Differential signaling comprises a pair of coupled, symmetrically opposite and operatively dependent electronic signals each driven by voltages of the same magnitude, but of opposite polarity with respect to a common ground. The drive voltages of each signal are of relatively low potential as compared to the core operating voltage of present day devices. The low-voltage pair of signals tends to create offsetting fields of electromagnetic interference from the flow of current within their respective conductors which tends to minimize inductive effects (and therefore corruption of signals) in adjacent signal lines. Differential signaling replaces all or as many single-end signals as possible throughout the device resulting in relatively lower power usage as compared to present devices.

Method to reduce integrated circuit power consumption by using differential signaling within the device

A method of communicating a data bit between memory devices is disclosed, having the steps of: indicating a first value of the data bit by transitioning, between state values, a first signal applied to a first communication line interconnecting the devices; and indicating a second value of the data bit by transitioning, between the state values, a second signal applied to a second communication line interconnecting the devices. Only one of the first and second signals may transition between the state values at any one time.

Method to transfer data without a clock or strobe signal

Modularized clock decoupling and signal delay management is provided for the purpose of reducing simultaneous binary signal switch-induced inductive voltage transients in lower voltage synchronous semiconductor devices. The voltage levels in low-voltage devices must be tightly maintained for proper transistor logic operations. Signal switching results in current changes on the power net of an IC. Current changes produce inductive voltage transients which propagate throughout the device and which can interfere with signal transmission and device operation. Relatively independent functioning circuits of an integrated circuit are isolated from the chip clock and each isolated circuit module is provided with its own independent, same-frequency, but slightly out-of-phase clock signal. Signal switching within any module is thus occurring out-of-phase with that of all other modules and, as a result, switch-associated voltage transients are limited to those associated with one module's circuits at a time.

Method to reduce inductive effects of current variations by internal clock phase shifting

The output of drivers which are used to drive the input signals to a multiplexed signal line are combined in a logic OR gate or a logic AND gate prior to connection to the input of the multiplexed line. The inactive state of drivers connected through a logic OR gate is set to 0 and the inactive state of drivers connected through a logic AND gate is set to 1. Bus contention between drivers is eliminated and the bandwidth of the multiplexed serial bus is increased because of the reduced wait time between driver transitions. Power dissipation in transition is reduced and the bus can have a programmable inactive state on a bus to allow for 1, 0 or High Z to indicate the inactive state.

Time division multiplexed serial bus with increased bandwidth

A programmable delay circuit ( ) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only way for satisfying timing requirements. Circuit ( ) includes a programmable delay chain ( ) connected to a hysteresis circuit ( ). A processor control signal is fed into the programmable delay chain ( ) which includes at least one switch ( ) and at least one resistive element ( ) connected together. A first feedback circuit ( ) connects the output of the programmable delay chain ( ) to the input (IN ) of the first embodiment ( ) to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit ( ) which provides a stable signal connects to an output driver ( ) for driving the processor control signal.

Programmable delay for processor control signals

A message-based memory system for Digital Signal Processor (DSP) storage expansion has a shared memory device connected to a number of DSPs through a packet communication bus. Each of the DSPs has a packet bus interface interconnected to the packet bus; and a messaging unit connected to the packet bus interface. The memory device interconnected to the packet bus can provide shared memory space for the DSPs to increase the amount of memory available to each DSP. The memory device can also be utilized to provide access to common information such as shared data or shared programing that may need to be run by multiple DSPs. The DSPs and the memory device communicate through the packet bus interface by generating packetized read and write requests.

Message-based memory system for DSP storage expansion

A reduced power dissipation integrated circuit. Power dissipation within a CMOS circuit is reduced by substitution of multi-level buses with several thresholds for binary state buses with a single threshold. A significant portion of an IC's power dissipation is consumed by the act of charging and discharging data and address busses within the IC because theses busses possess the highest capacitances of any of the nodes within the part. The present invention uses a series of thresholds from a minimum voltage to a maximum voltage. Below the minimum threshold voltage Vref1, the logic state would be &ldquo;0&rdquo;. Above the maximum threshold voltage Vrefn, the logic state would be &ldquo;n&rdquo;. A series of defined thresholds, Vref1, Vref2, . . . Vrefn, between the minimum and maximum voltages define a series of logic states 0, 1, 2 . . . n&plus;1 between 0 and n&plus;1.

Structure and method for reduction of power consumption in integrated circuit logic

An approach to reduce noise associated with ground bounce in integrated circuits containing CMOS gates and drivers is provided. Typical CMOS gates and drivers consist of complementary pairs of MOS gates. As the CMOS driver input transitions from high to low or low to high, there is a brief period during which both gates of a CMOS are conductive. When both gates are on, voltage and/or current spikes can occur from a variety of sources, including parasitic inductance between the gate and its external power supply. Disruptions, bounces, and sinks in voltage and/or current can create noise which can be propagated throughout a chip, potentially resulting in operational errors. The present invention adds a high and low reference voltage and two or more pairs of CMOS gates to each gate's circuit to dynamically add charge and/or draw charge from the CMOS gate as needed to reduce ground bounce and noise.

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Germantown, MD, United States of America

Keith Krasnansky