Bae Systems Information and Electronic Systems Integration Inc.

Ovonyx Inc.

Bae Systems Information and Electronics Systems Integration Inc.

Keith K Sturcken

Thomas J McIntyre

John A Hughes

John C Rodgers

Steven J Wright

Santos H Nazario-Camacho

Sheila J Konecke

Christy A Hagerty

John D Davis

Tushar T Shah

Tushar K Shah

Peter W Spreen

Dale A Rickard

Jason F Ross

Yannick C Morel

Andrew T Pomerene

Michael J O'Connor

Alan F Dennis

Timothy Whalen

Steve Hudgens

Clint J Novotny

Thomas E Love

Jamie A Bernard

Peter M Wallace

Jane O Gilliam

Lori D Dennis

Jeffrey Montag

Alan M Berard

George Clemen

Saint Nazario-Camacho

Kenneth J Cross

A hermetically sealed electronics module includes a core IC installed on a substrate. A collar surrounds the core IC and is sealed to the substrate and to a lid, forming a sealed chamber. A heat spreader bonded to an internal surface of the lid extends downward into proximal thermal contact with the core IC. A thin layer of TIM can be applied between the heat spreader and core IC. The heat spreader does not overlap any tall components that extend above the core IC, and can extend over regions adjacent to the core IC. Tall components can be limited to a periphery of the chamber, and/or the heat spreader can include openings that surround central tall components. The heat spreader can be soldered or welded to the lid over an entire upper surface of the heat spreader. X-ray and/or CSAM scanning can detect heat spreader bonding flaws.

Hermetically sealed electronics module with enhanced cooling of core integrated circuit

A multi-chip module hybrid integrated circuit (MCM-HIC) provides cold spare support to an apparatus comprising a plurality of ICs and/or other circuits that are not cold spare compliant. At least one core IC and at least one cold spare chiplet are installed on an interconnecting substrate having a plurality of power zones to which power can be applied and withdrawn as needed. When powered, the cold spare chiplets serve as mediators and interfaces between the non cold spare compliant circuits. When the cold spare chiplets are at least partly unpowered, they protect all interconnected circuits, and ensure that interconnected circuits that remain powered are not hindered by unpowered interconnected circuits. Cold spare chiplets can extend across boundaries between power zones. External circuits can be exclusively interfaced to a subset of the power zones. Separate power circuits within a power zone can be sequenced during application and withdrawal of power.

Multi-chip module hybrid integrated circuit with multiple power zones that provide cold spare support

A microwave module is described. The microwave module includes a base bracket, a window plate and a lid. The base bracket is configured to contain a photoconductive switch, a radio-frequency transformer and dielectric oil. The window plate, which is transparent to optical light, covers a first portion of the base bracket in which the photoconductive switch is located. The window plate is sealed to the base bracket. The lid, which includes a cutout to allow the radio-frequency transformer to pass through the lid, covers a second portion of the base bracket in which the radio-frequency transformer is located. The window plate is sealed to the base bracket, and the lid is sealed to the window plate, the base bracket and the radio-frequency transformer to contain the dielectric oil within the microwave module.

Packaging for high-power microwave module

An apparatus for cooling electronic devices to be used in the vacuum of space is described. a window frame is provided as packaging for an electronic device having a substrate and a chip. The window frame includes an opening to allow a heat pipe to be in direct contact with a backside of the chip. The window frame is hermetically sealed to the backside of the chip. The window frame is also welded to a kovar ring located on the backside of the chip to provide a hermetic seal between the window frame and the substrate.

Method and apparatus for cooling electonic components

A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.

Method for fabricating solder columns for a column grid array package

A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed.

Devices and methods for stacking individually tested devices to form multi-chip electronic modules

An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate. The non-uniformity of length in the wire columns reduces stress in the package leads after attachment of the package to a carrier substrate, such as a printed circuit board.

Isostress grid array and method of fabrication thereof

An apparatus for providing thermal management on high-power integrated circuit devices is disclosed. Initially, contacts to active devices are formed. Phase change materials are then applied over potential hot spots that can be formed by the active devices. A layer of high-thermally conductive materials is deposited over the phase change materials. The layer of high-thermally conductive materials and the phase change materials are subsequently etched according to a pattern. A layer of passivation conductive vias is subsequently applied to the phase change materials to complete the formation of phase change heatsinks.

Method and apparatus for providing thermal management on high-power integrated circuit devices

The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming current to a resistor which is in thermal contact with the chalcogenide material. The semiconductor device may be used as memory element or as a programmable fuse.

Programmable resistance memory element with indirect heating

A high-density electronics package compromises a chip-stack having a plurality of ICs. Oblong-shaped bumps comprising an electrically-conductive bonding material are disposed along one side of each IC in the chip-stack. The one side of each IC bearing the bumps is aligned with the bump-bearing side of all other ICs in the chip-stack. A portion of each oblong-shaped bump extends beyond the edge of its host IC. This portion of each bump is available to electrically and mechanically connect the chip stack to the next packaging layer, such as a printed circuit board.

Article comprising a multi-layer electronic package and method therefor

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Method for manufacturing a programmable chalcogenide fuse within a semiconductor device

A method of forming a plurality of micro column interconnection structures on a semiconductor includes providing a semiconductor layer. A photoresist layer is formed on the semiconductor layer. A plurality of cavities are etched in the photoresist layer. The plurality of cavities extend through the photoresist layer to the semiconductor layer. Solder is deposited in the plurality of cavities, thereby forming a plurality of micro columns of solder.

Method for forming a micro column grid array (CGA)

Methods for manufacturing microchips are provided. A plurality of alternating metallic wiring-layers and non-metallic layers, terminating with a metallic wiring-layer, are formed on a wafer. A plurality of vias is formed for electrically interconnecting various metallic wiring-layers. A plurality of electrically conducting pads is formed adjacent various vias. A passivation layer is formed adjacent the terminal metallic wiring-layer and the plurality of conducting pads. A portion of the passivation layer is removed to expose the plurality of conducting pads. A layer is formed adjacent the passivation layer and the plurality of exposed conducting pads for protecting the microchip against electromagnetic radiation. A portion of the protective layer is removed to expose the plurality of conducting pads. Each conducting pad is electrically isolated from the protective layer. An electrically conducting bump is formed on each conducting pad.

Insitu radiation protection of integrated circuits

A microchip having a passivation layer on an electrically active surface; a multitude of electrically conducting protuberances for electrically coupling the active surface to a substrate; a layer on the passivation layer for protecting against electromagnetic radiation; and a layer on an electrically inactive surface of the microchip for protecting against electromagnetic radiation.

Growing community of inventors

Nokesville, VA, United States of America

Keith K Sturcken