International Business Machines Corporation

Keith K Slack

Ronald Eugene Bodner

Thomas L Crooks

Israel B Magrisso

David Otto Lewis

William E Hammer

Thomas S Robinson

Richard T Turner

John W Reed

Richard S Smith

John E Guest

Terrell A Poland

J Warren McCullough

Mario N Cianciosi

Dale N Reynolds

Synchronous and conditional inter-program control apparatus in a computer system is structured to temporarily suspend execution of an invoking program and to transfer processor control to an invoked program. Such transfer is initiated by a transfer initiation means which interacts with a function control means of a function control array and provides symbolic identification of an entry point in the invoked program and conditionally continuing the transfer mechanism. The function control means addresses call return elements (CRE's) when it is in an execute mode but transfers processor control back to the invoking program when it is in a by-pass mode. CRE's that are in an available, data-receivable state are chained on an available call return queue (ACQ) and may be removed therefrom and placed on a task dispatching element (TDE) on an as-needed basis through a receive message mechanism. Active CRE's contain a status save means for storing the state of the invoking program during execution of the invoked program. In the event there are no active CRE's available for such storage, a task switch occurs, and the current TDE, i.e., the invoking program, is inserted on a wait list of the ACQ where it remains until a CRE becomes available. When the CRE becomes available, the invoking program TDE is removed from the ACQ wait list and inserted in priority sequence on the task dispatching queue (TDQ). Once a CRE is made available to the TDE, the transfer initiation means is restarted. At the termination of the execution of the invoked program, a transfer return means transfers processor control back to the invoking program and inserts the CRE onto the ACQ. The invoking program then commences execution at the next sequential instruction.

Synchronous and conditional inter-program control apparatus for a

In a paged, virtual memory computer system an apparatus is provided for enabling I/O device adapters to request the CPU to allocate or resolve virtual pages into main storage pages as required for I/O data transfers. The I/O adapter provides the channel virtual address information specifying the requested page and channel function information which indicates whether the requested page is to be transferred from secondary storage into main storage or merely allocated as a page in main storage. The channel forms the virtual address information and the channel function information into a page request function event which is stored in an I/O event stack in main storage for retrieval and processing by the CPU.

Allocating and resolving next virtual pages for input/output

Data transfers between input/output (I/O) devices and a central processing unit (CPU) take place under instruction or base cycle steal control a byte at a time where the I/O device attachments connect to ports and the ports connect to the CPU. Data transfer can be synchronous or asynchronous. The port involved in the data transfer sends out a device address and command information simultaneously on port data bus out and command bus out, respectively, to the I/O attachments. The addressed I/O device can respond any time within a predetermined time interval. If an I/O device does not respond within the time interval, a blast condition generated by the port causes the I/O attachments to clear the busses between it and the port. During execution of an I/O instruction, the CPU clock is first held in a particular time state while phase clocks and port clocks continue to run and synchronization between the port and I/O attachment is taking place. Upon completion of the synchronization sequence, the port generates an advance time signal to the CPU to advance the CPU clock. The CPU clock runs and the storage clock can be activated depending upon the type of I/O instruction being executed, the CPU clock runs until it reaches a second particular time state and then remains at that particular time state until the port again generates an advance time signal to the CPU. The activity taking place as the CPU clock is advancing depends upon the type of I/O instruction, but generally a data transfer occurs, and the data is entered into or transferred from local storage registers or main or control storage. The extended second particular time state is used for a de-synchronization sequence between the port and I/O attachment.

I/O data transfer control system

Control circuitry in a computer system is responsive to an allow cycle steal signal from an I/O attachment operating in a burst or dedicated data transfer mode and generates control signals whereby the next data storage cycle is made available to an I/O device which is also capable of operating in a cycle steal mode. Upon completion of the next storage cycle, the operation reverts to burst mode and the I/O attachment operating in the burst mode is granted ensuing data storage cycles until it relinquishes a storage cycle to an I/O device capable of using and having a need for it.

Cycle interleaving during burst mode operation

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Rochester, MN, United States of America

Keith K Slack