National Semiconductor Corporation

Atheros Communications, Inc.

Keith K Onodera

William John McFarland

David Kuochieh Su

Manolis Terrovitis

John S Thomson

Arie Shor

Masoud Zaragari

Alex B Djenguerian

Shu-ing Ju

A dual band radio is constructed using a primary and secondary transceiver. The primary transceiver is a complete radio that is operational in a stand alone configuration. The secondary transceiver is a not a complete radio and is configured to re-use components such as fine gain control and fine frequency stepping of the primary transceiver to produce operational frequencies of the secondary transceiver. The primary transceiver acts like an intermediate frequency device for the secondary transceiver. Switches are utilized to divert signals to/from the primary transceiver from/to the secondary transceiver. The switches are also configured to act as gain control devices. Antennas are selected using either wideband or narrowband antenna switches that are configured as a diode bridge having high impedance at operational frequencies on control lines that bias the diodes.

Dual frequency band wireless LAN

A differential amplifier can include input transistors for receiving a differential input signal and an inductor connected to the input transistors. The inductor can protect a voltage supply from radio frequency in the differential input signal. The accuracy of this differential amplifier can be significantly improved by including a bias network. This bias network advantageously allows a bias current in the input transistors to be set independently of a voltage drop across the inductor.

Transistor biasing independent of inductor voltage drop

A system including a reference oscillator, a controlled oscillator, a digital phase detector, and a digital loop filter uses a method for matching a first oscillation frequency of the controlled oscillator with a second oscillation frequency of the reference oscillator by variably selecting different capacitances and/or resistances of the controlled oscillator using switches. The first and second oscillation frequencies are provided to the digital phase detector, where they are compared to determine an output signal which is indicative of the difference between the first and second frequencies. The output signal is transmitted to a digital loop filter, which converts the output signal into control words. The control words are sent to the controlled oscillator so that the first oscillation frequency can be varied as needed. The controlled oscillator may be a capacitor controlled oscillator (CCO), a resistor controlled oscillator (RCO), or a resistor-capacitor controlled oscillator (RCCO).

Capacitor and resistor controlled oscillator timing lock loop for

A drive circuit suitable for driving an inductive load such as an isolation transformer is disclosed having a driver stage and associated feedback circuitry. The driver stage has at least one output for connecting to the load and is switchable between a drive mode and an idle mode of operation. In the drive mode of operation, the driver stage produces a data output signal at the output which corresponds to a data input signal received by the driver stage. In the idle mode, the driver stage produces an idle signal, in response to a control signal, which functions to discharge the conductive load. The feedback circuit produces the control signal in response to the idle signal and adjusts the control signal so that the idle output signal will approach a predetermined neutral level. The inductor will proceed to discharge and, once discharged, will shift the idle voltage. The shift in voltage will cause the feedback action to terminte, thereby preventing the feedback action from introducing charging current into the inductor which would adversely effect the transmission of further data.

Driver circuit with feedback for limiting undershoot/overshoot and method

A totem-pole transistor circuit in the output stage of a logic device includes, in the base circuit of the current sink transistor, a discharge transistor responsive to each transition of a circuit input signal for discharging the parasitic base capacitance of the sink transistor, and a circuit for delaying the delivery of the input signal to the discharge transistor. The delay results in postponing the transition of the discharge transistor from one operational state to another. This causes the transitions of the discharge transistor to lag the transitions of the totem-pole pair which occur simultaneously with input signal changes. Thus, the discharge transistor is held on for a period of time sufficient to discharge the parasitic capacitance when the current-sink transistor turns off. This speeds up the turn-off of the sink transistor. After the period elapses, the discharge transistor turns off. Then, when base current is supplied to the current-sink transistor to turn it on, the discharge transistor is held off for an amount of time during which all of the base current is provided to the current-sink transistor, causing it to be quickly switched on. Then the discharge transistor is turned on, permitting it to discharge the parasitic capacitance of the current-sink transistor at the next input signal transition.

Growing community of inventors

Berkeley, CA, United States of America

Keith K Onodera