Lsi Logic Corporation

Applied Materials, Inc.

Novellus Systems Incorporated

Lam Research Corporation

Lst Logic Corporation

Keith J Hansen

Jaim Nulman

Seshadri Ramaswami

Glen T Mori

Murali K Narasimhan

Vikram Pavate

Michal Danek

Richard Alan Gottscho

Keith B Wells

Kapil Umesh Sawlani

Paul Poenisch

Defects on a substrate comprising electronic components can be classified with a computational defect analysis system that may be implemented in multiple stages. For example, a first stage classification engine may process metrology data to produce an initial classification of defects. A second stage classification engine may use the initial classification, along with manufacturing information and/or prior defect knowledge to output probabilities that the defects are caused by one or more potential sources.

Defect classification and source analysis for semiconductor equipment

Fault detection apparatuses and methods for detecting a processing or hardware performance fault of a semiconductor production tool have been provided. In an exemplary embodiment, a method for detecting a fault of a semiconductor production tool includes sensing a signal associated with a test component of the production tool during operation of the production tool and converting the signal to an electronic test signal. A prerecorded signature signal corresponding to the test component is provided and the test signal and the prerecorded signature signal are compared.

Fault detection apparatuses and methods for fault detection of semiconductor processing tools

Improved targets for use in DC_magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.

Method for manufacturing metal sputtering target for use in DC magnetron so that target has reduced number of conduction anomalies

Target for use in magnetron sputtering of aluminum for forming metallization films having low defect densities and methods for manufacturing and using such target

Improved targets for use in DC.sub.-- magnetron sputtering of aluminum or like metals are disclosed for forming metallization films having low defect densities. Methods for manufacturing and using such targets are also disclosed. Conductivity anomalies such as those composed of metal oxide inclusions can induce arcing between the target surface and the plasma. The arcing can lead to production of excessive deposition material in the form of splats or blobs. Reducing the content of conductivity anomalies and strengthening the to-be-deposited material is seen to reduce production of such splats or blobs. Other splat limiting steps include smooth finishing of the target surface and low-stress ramp up of the plasma.

Target for use in magnetron sputtering of aluminum for forming

In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas. Other process and apparatus features enable higher bonding strength between the silicon surface and the formed barrier layer contacting the silicon surface and enable a higher purity content of the processing gases as well as improved diffusion of processing gases when injected into the processing chamber.

Purging gas control structure for CVD chamber

In-situ etch of CVD chamber

In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas. Other process and apparatus features enable higher bonding strength between the silicon surface and the formed barrier layer contacting the silicon surface and enable a higher purity content of the processing gases as well as improved diffusion of processing gases when injected into the processing chamber.

Gas control technique for limiting surging of gas into a CVD chamber

A method for filtering process gases prior to said process gases being allowed to enter a CVD chamber is provided in order to ensure high purity of the process gases. In one embodiment, the process gases are filtered with a first filter located in a first section of a gas line being isolated by valves at both ends of the gas line section. Further filtering by a second filter occurs in a downstream gas line section.

Filtering technique for CVD chamber process gases

Tungsten deposition process for low contact resistivity to silicon

Walls of a CVD chamber are automatically controlled to be heated to above 65.degree. C. during etching of the chamber walls with NF.sub.3. Any condensation of reaction products on the chamber walls is avoided, since, at the relatively high chamber wall temperature, these reaction products are volatile and are purged away with the NF.sub.3. The apparatus is programmed to automatically carry out this heating and gas injecting process.

Apparatus for performing in-situ etch of CVD chamber

During the cleaning of CVD chamber walls with an etch gas of NF.sub.3, the reaction chamber walls are heated to above 65.degree. C. while maintaining a relatively low chamber pressure during etching of the chamber with NF.sub.3. Any reaction of the NF.sub.3 with the quartz (SiO.sub.2) walls of the chamber, and with any reaction by-products remaining in the chamber, will not condense on the walls of the chamber, since, at this relatively high temperature, these reaction products will be volatile and will be purged away with the NF.sub.3.

Method for performing in-situ etch of a CVD chamber

In one embodiment, an apparatus programmed to automatically form a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas. Other process and apparatus features enable higher bonding strength between the silicon surface and the formed barrier layer contacting the silicon surface and enable a higher purity content of the processing gases as well as improved diffusion of processing gases when injected into the processing chamber.

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San Jose, CA, United States of America

Keith J Hansen