Ampex Corporation

Ampex Systems Corporation

Keith J Bertrand

A low cost, high speed data storage system provides word-by-word stale data detection while avoiding the need to both read and write a single memory location during a memory read operation. Two flag data storage bits are provided for each word location in addition to the normal data storage bits. As blocks of data are received by the storage system one of the two flag bits is assigned to the block on an alternating basis. Upon writing data to an address location, an assigned flag bit is written to a first state to indicate valid data. When reading, the corresponding assigned flag bit is output as a stale or invalid data signal and the nonassigned flag bit is set to a second state different from the first state in preparation for the next block of data.

Data storage system with stale data detector and method of operation

The data unpacker receives packed parallel input data words having a fixed width of m bits, and it outputs parallel data words having a variable width of n bits. An input register stores the received words and applies them to a bit shifter. The bit shifter shifts the received data by a number of bit positions indicated by a shift control signal, and the shifted data is output therefrom as a parallel output word having n valid bits. The number n for each output word is received by the unpacker as a binary number. When n.gtoreq.m, a most significant (MSB) bit portion of that number is applied as first MSB control signal. The least significant bit (LSB) portion of n is applied to an adder which adds subsequently received LSB portions to provide a running sum. When the running sum is equal to or greater than m, the adder provides a second MSB control signal, corresponding to the most significant bit of the running sum. The least significant bit portion of the running sum is applied to the bit shifter as the shift control signal. A logic circuit receives the first and second control MSB control signal and it provides in response to either of these signals a READY FOR DATA control signal indicating that the input register is ready to receive the next input word, and a DATA VALID OUT control signal indicating that the bit shifter is ready to output the parallel output word.

Data unpacker using a pack ratio control signal for unpacked parallel

The data packer receives n-bit wide parallel data words, and it outputs m-bit wide packed parallel data words, where n is a variable and may change during the operation, and m is a fixed integer. The input data words are applied to a bit shifter and therefrom to a data output circuit where they are stored until the necessary m bits are obtained. In the preferred embodiment a control circuit which comprises an adder, receives information indicating the number of valid data bits in each input word, and it provides a running sum of the number of received valid data bits. When the number of bits in an input word is equal to or greater than m, the control circuit provides a first control signal which occurs simultaneously with an m-bit wide packed parallel output word provided by the output circuit. Any number of input bits which is less than m is added to a remainder of a previous sum which is also less than m. When the thusly obtained sum is equal to or greater than m, a second control signal is provided which also occurs simultaneously with an m-bit wide packed word provided by the output circuit. The control circuit applies the running sum as a third control signal to the bit shifter, effecting shift of the next received data word by a number of bit positions corresponding to that sum. The number indicated by the third control signal also corresponds to the number of bits currently stored in the output circuit.

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Sunnyvale, CA, United States of America

Keith J Bertrand