International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Keith Howard Tabakman

Judson Robert Holt

Viorel C Ontalus

Eric C Harley

Henry K Utomo

Viraj Yashawant Sardesai

Abhishek Dube

Rishikesh Krishnan

Yue Ke

Matthew W Stoker

Hui Zang

Kathryn Turner Schonenberg

Linda R Black

Veeraraghavan S Basker

Ramachandra Divakaruni

Guowei Xu

Sameer Hemchand Jain

Alexander Reznicek

Kevin K Chan

Thomas N Adam

Guillaume Bouche

Michael Vincent Aquilino

Suraj Kumar Patil

Zhiguo Sun

Patrick D Carpenter

Eric C T Harley

Bo Bai

Kangguo Cheng

Ruilong Xie

Devendra K Sadana

Lawrence Alfred Clevenger

Stephen W Bedell

Reinaldo Ariel Vega

Dominic Joseph Schepis

Ravikumar Ramachandran

Zhengwen O Li

Brian Joseph Greene

Jinping Liu

Jiehui Shu

Sipeng Gu

Daniel J Jaeger

Dan Moy

Malek Ben Salem

Huiling Shang

Xintuo Dai

Man Gu

Kai Zhao

Shwu-Jen Jeng

Katsunori Onishi

Gary Walter Behm

Charlotte DeWan Adams

Hasan Munir Nayfeh

Tao Han

Ishtiaq Ahsan

Yue J Li

Dongyue Yang

Junsic Hong

Thomas P Moyer

Brian M Trapp

Jeffrey Chee

Lin Hu

Christopher Nassar

Jeremy John Kempisty

Xiaoming Yang

Asli Sirman

Guanchen He

Xueli Hao

Andrew Alexander McKnight

A device and method for forming a semiconductor device includes forming a gate structure on a channel region of fin structures and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

FinFET with dielectric isolation after gate module for improved source and drain region epitaxial growth

A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Source/drain contact depth control

The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.

Middle of line structures

A method, FET structure and gate cut structure are disclosed. The method forms a gate cut opening in a dummy gate in a gate material layer, the gate cut opening extending into a space separating a semiconductor structures on a substrate under the gate material layer. A source/drain region is formed on the semiconductor structure(s), and a gate cut isolation is formed in the gate cut opening. The gate cut isolation may include an oxide body. During forming of a contact, a mask has a portion covering an upper end of the gate cut isolation to protect it. The gate cut structure includes a gate cut isolation including a nitride liner contacting the end of the first metal gate conductor and the end of the second metal gate conductor, and an oxide body inside the nitride liner.

Gate cut first isolation formation with contact forming process mask protection

A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.

Third type of metal gate stack for CMOS devices

In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

FinFET with high-k spacer and self-aligned contact capping layer

Embodiments of the disclosure provides an apparatus for aligning layers of an integrated circuit (IC), the apparatus including: an insulator layer positioned above a semiconductor substrate; a first diffraction grating within a first region of the insulator layer, the first diffraction grating including a first grating material within the first region of the insulator layer; and a second diffraction grating within a second region of the insulator layer, the second grating including a second grating material within the second region of the insulator layer, wherein the second grating material is different from the first grating material, and wherein an optical contrast between the first and second grating materials is greater than an optical contrast between the second grating material and the insulator layer.

Apparatus and method for aligning integrated circuit layers using multiple grating materials

A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.

Methods of forming a gate structure-to-source/drain conductive contact and the resulting devices

A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.

Semiconductor devices with robust low-k sidewall spacers and method for producing the same

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

Contact line having insulating spacer therein and method of forming same

Growing community of inventors

Fishkill, NY, United States of America

Keith Howard Tabakman