International Business Machines Corporation

Keith G Barkley

Peter J Camporese

Majid Ghafghaichi

Kwok Fai Eng

Yelandur R Gopalakrishna

Albert J Tzou

A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires increases for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire. In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it. The process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools.

Contract methodology for concurrent hierarchical design

This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order.

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Poughquaq, NY, United States of America

Keith G Barkley