Texas Instruments Corporation

Keith Eric Sanborn

Jerry Doorenbos

Srikanth Vellore Avadhanam Ramamurthy

Dwight David Griffin

Mina Raymond Naguib Nashed

Erika Lynn Mazotti

Wai Lee

Steve Edward Harrell

Vadim Valerievich Ivanov

Johnnie F Molina

An electronic device, e.g. a trimmable resistor, includes a plurality of fused resistors, each fused resistor including one or more doped resistive regions formed in a semiconductor substrate. The doped resistive regions may be thermistors. Each fused resistor further includes a corresponding one of a plurality of fusible links. A first terminal of each of the fused resistors is connected to a first terminal of the corresponding fusible link. First and second interconnection buses are located over the substrate, with the first interconnection bus connecting to a second terminal of each of the fused resistors, and the second interconnection bus connecting to a second terminal of each of the fusible links. The plurality of fused resistors have resistance values that form an exponential progression.

Resistor with exponential-weighted trim

In some examples, a sigma-delta analog-to-digital converter (ADC), comprises a first set of switches configured to receive a first voltage signal; a second set of switches coupled to the first set of switches at a first node and a second node, the second set of switches configured to receive a second voltage signal; an integrator including a first input sampling capacitor coupled to the first node and a second input sampling capacitor coupled to the second node, wherein the integrator configured to generate a first output signal. The sigma-delta ADC further comprises a comparator coupled to the integrator and configured to generate a second output signal based on the first output signal; and a controller unit having a first counter, a second counter, and a processor, the controller unit coupled to the first and second sets of switches, the integrator, and the comparator.

Temperature sensing with bandgap sensor input to sigma-delta ADC

Sigma-delta analog-to-digital converter with multiple counters

A first-order sigma-delta analog-to-digital converter includes an input terminal, an integrator circuit, a comparator, and control circuitry. The input terminal is configured to receive a unipolar input signal to be digitized. The integrator circuit is coupled to the input terminal. The comparator is coupled to an output of the integrator circuit. The control circuitry is coupled to the integrator circuit and the comparator. The control circuitry is configured to equalize time that an output signal generated by the integrator circuit is greater than zero and time that the output signal generated by the integrator circuit is less than zero during digitization of the unipolar input signal.

First-order sigma-delta analog-to-digital converter

A power-on reset (POR) circuit includes a first transistor (MP) having a source coupled to a first supply voltage (V) and a gate coupled to a second supply voltage (GND). A resistor (R) has a first terminal coupled by a depletion mode transistor (JP) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger () has an input coupled to receive a first signal (V) on a conductor () coupled to the second terminal of the resistor and a terminal of a capacitor (C), for producing an output voltage (V) representative of a power-on reset signal (V) in response to an interruption of the first supply voltage (V).

Low current power-on reset circuit and method

A circuit producing a reversed bandgap reference voltage circuit Vincludes first and second resistors coupled as a voltage divider between ground and a first conductor, a base of a first transistor being coupled to the voltage divider to produce a first voltage V(1+1/M) between the first conductor and ground, M being a ratio of the resistances of the first and second resistors. A third resistor is coupled between a base of the second transistor and ground to produce a second voltage V+Vbetween the second conductor and ground. First circuitry forces the collector current of the first transistor to be equal to the collector current of the second transistor, and second circuitry forces the first voltage V(1+1/M) to be equal the second voltage V+V. One of the first circuitry and second circuitry includes an operational amplifier coupled to effectuate the forcing.

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Tucson, AZ, United States of America

Keith Eric Sanborn