International Business Machines Corporation

Kozio, Inc.

Keith Edward Short

Joseph G Skazinski

Noel Simen Otterness

William A Brant

William G Deitz

A system and method for testing input and output paths connected to an embedded processor. Specialized test software operating on the embedded processor creates one or more test workers or threads, each having a specific routine to perform, which are executed in parallel, stressing various communication paths. The results may be analyzed to help in many different ways during the life cycle of the device with the embedded controller.

Embedded Test I/O Engine

A method and apparatus for controlling a memory system comprising a plurality of controllers connected by a fibre channel arbitrated loop to provide transparent failover and failback mechanisms for failed controllers. The controllers are adapted to transfer data between a data storage system and at least one host computer in response to instructions therefrom. In the method, a unique identifier is provided to each controller . The operation of the controllers is then monitored and, when a failed controller is detected, a failover procedure is performed on a surviving controller. The failover procedure includes disabling the failed controller and instructing the surviving controller to assume the identity of the failed controller. Thus, the surviving controller is capable of responding to instructions addressed to it and instructions addressed to the failed controller, and the failure of the failed controller is transparent to the host computer . A computer program and a computer program product for implementing the method are also provided.

Method and apparatus for providing a raid controller having transparent failover and failback

This inventive provides a multiple level cache structure and multiple level caching method that distributes I/O processing loads including caching operations between processors to provide higher performance I/O processing, especially in a server environment. A method of achieving optimal data throughput by taking full advantage of multiple processing resources is disclosed. A method for managing the allocation of the data caches to optimize the host access time and parity generation is disclosed. A cache allocation for RAID stripes guaranteed to provide fast access times for the XOR engine by ensuring that all cache lines are allocated from the same cache level is disclosed. Allocation of cache lines for RAID levels which do not require parity generation and are allocated in such manner as to maximize utilization of the memory bandwidth is disclosed. Parity generation which is optimized for use of the processor least utilized at the time the cache lines are allocated, thereby providing for dynamic load balancing amongst the multiple processing resources, is disclosed. An inventive cache line descriptor for maintaining information about which cache data pool the cache line resides within, and an inventive cache line descriptor which includes enhancements to allow for movement of cache data from one cache level to another is disclosed. A cache line descriptor with enhancements for tracking the cache within which RAID stripe cache lines siblings reside is disclosed. System, apparatus, computer program product, and methods to support these aspects alone and in combination are also provided.

Growing community of inventors

Lafayette, CO, United States of America

Keith Edward Short