International Business Machines Corporation

Globalfoundries Inc.

King Abdulaziz City for Science and Technology

Egypt Nanotechnology Center

S.o.i.tec Silicon on Insulator Technologies

Keith E Fogel

Devendra K Sadana

Stephen W Bedell

Paul Alfred Lauro

Jeehwan Kim

Alexander Reznicek

Da-Yuan Shih

Brian Samuel Beaman

Joel Pereira De Souza

Ghavam G Shahidi

Maurice Heathcote Norcott

Davood Shahrjerdi

Augustin J Hong

Katherine Lynn Saenger

Pouya Hashemi

Ning Li

George Frederick Walker

Anthony Gene Domenicucci

Praneet Adusumilli

Oscar Van Der Straten

Huajie Chen

Kangguo Cheng

Bahman Hekmatshoartabari

Karthik Balakrishnan

Thomas N Adam

Daniel Peter Morris

Christos Dimitrios Dimitrakopoulos

John Albrecht Ott

Brent A Wacaser

Bahman Hekmatshoar-Tabari

Haizhou Yin

Gareth Geoffrey Hougham

Steven John Koester

Chun-Yung Sung

Shogo Mochizuki

Kuen-Ting Shiu

Pranita Kerber

Edward William Kiewra

Bruce Bennett Doris

Veeraraghavan S Basker

Sivananda K Kanakasabapathy

Dominic Joseph Schepis

Jae-Woong Nah

Cheng-Wei Cheng

Robert H Dennard

Qiqing Christine Ouyang

Sung Kwon Kang

Shahab Siddiqui

Paul David Agnello

Christopher Carr Parks

Henry Atkinson Nye, Iii

Ali Khakifirooz

Effendi Leobandung

Steven J Holmes

Haining S Yang

Mark Charles Hakey

Judson Robert Holt

Jack Oon Chu

Eugene John O'Sullivan

Supratik Guha

Dirk Pfeiffer

Brian Joseph Greene

Fuad Elias Doany

Xiao Hu Liu

George Stojan Tulevski

Alfred Viehbeck

Jeffrey Curtis Hedrick

James Bowler Hannon

Leathen Shi

Martin O Sandberg

Vivekananda P Adiga

David Andrew Lewis

Ko-Tao Lee

Stanley Joseph Whitehair

Can Bayram

Kam-Leung Lee

John J Ritsko

James L Hedrick

Michael J Ellsworth, Jr

Madhusudan K Iyengar

Robert E Simons

Richard C Chu

Levi A Campbell

Roger R Schmidt

Balasubramanian Pranatharthiharan

Jeng-Bang Yau

Amlan Majumdar

Shreesh Narasimha

Tze-Chiang Chen

Jane M Shaw

Markus Brink

Muthumanickam Sankarapandian

Donald Francis Canaperi

John Christopher Arnold

Harold John Hovel

David Brian Mitzi

Ho-Ming Tong

Sandip Tiwari

Yanning Sun

Charan V Surisetty

Systems and techniques that facilitate spurious junction prevention via in-situ ion milling are provided. In various embodiments, a method can comprise forming a tunnel barrier of a Josephson junction on a substrate during a shadow evaporation process. In various instances, the method can further comprise etching an exposed portion of the tunnel barrier during the shadow evaporation process. In various embodiments, the shadow evaporation process can comprise patterning a resist stack onto the substrate. In various instances, the etching the exposed portion of the tunnel barrier can leave a protected portion of the tunnel barrier within a shadow of the resist stack. In various instances, the shadow of the resist stack can be based on a direction of the etching the exposed portion of the tunnel barrier. In various embodiments, the shadow evaporation process can further comprise depositing a first superconducting material on the substrate after the patterning the resist stack, oxidizing a surface of the first superconducting material to form the tunnel barrier, and depositing a second superconducting material over the protected portion of the tunnel barrier to form a Josephson junction. In various instances, the etching the exposed portion of the tunnel barrier can occur after the oxidizing the surface of the first superconducting material and before the depositing the second superconducting material.

Spurious junction prevention via in-situ ion milling

A structure including a three-dimensionally stretchable single crystalline semiconductor membrane located on a substrate is provided. The structure is formed by providing a three-dimensional (3D) wavy silicon germanium alloy layer on a silicon handler substrate. A single crystalline semiconductor material membrane is then formed on a physically exposed surface of the 3D wavy silicon germanium alloy layer. A substrate is then formed on a physically exposed surface of the single crystalline semiconductor material membrane. The 3D wavy silicon germanium alloy layer and the silicon handler substrate are thereafter removed providing the structure.

Three-dimensionally stretchable single crystalline semiconductor membrane

A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried dielectric therebetween. A device channel is formed in the thin semiconductor layer. Source and drain regions are formed at opposing positions relative to the device channel. The source and drain regions include an n-type material deposited on the buried dielectric within a thickness of the thin semiconductor layer. A gate structure is formed over the device channel.

Leakage-free implantation-free ETSOI transistors

A semiconductor structure is provided that includes non-metal semiconductor alloy containing contact structures for field effect transistors (FETs), particularly p-type FETs. Notably, each non-metal semiconductor alloy containing contact structure includes a highly doped epitaxial semiconductor material directly contacting a topmost surface of a source/drain region of the FET, a titanium liner located on the highly doped epitaxial semiconductor material, a diffusion barrier liner located on the titanium liner, and a contact metal portion located on the diffusion barrier liner.

Structure to enable titanium contact liner on pFET source/drain regions

A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

MOSFET with ultra low drain leakage

A method of making a Josephson junction for a superconducting qubit includes providing a substructure having a surface with first and second trenches perpendicular to each other defined therein. The method further includes evaporating a first superconducting material to deposit the first superconducting material and evaporating a second superconducting material to deposit the second superconducting material in the first trench to provide a first lead, and forming an oxidized layer on the first and second superconducting materials. The method includes evaporating a third superconducting material at an angle substantially perpendicular to the surface of the substructure to deposit the third superconducting material in the second trench without rotating the substructure to form a second lead. A vertical Josephson junction is formed at the intersection of the first and second trenches electrically connected through the first lead and through the second lead.

Junction fabrication method for forming qubits

A photovoltaic device and method include a doped germanium-containing substrate, an emitter contact coupled to the substrate on a first side and a back contact coupled to the substrate on a side opposite the first side. The emitter includes at least one doped layer of an opposite conductivity type as that of the substrate and the back contact includes at least one doped layer of the same conductivity type as that of the substrate. The at least one doped layer of the emitter contact or the at least one doped layer of the back contact is in direct contact with the substrate, and the at least one doped layer of the emitter contact or the back contact includes an n-type material having an electron affinity smaller than that of the substrate, or a p-type material having a hole affinity larger than that of the substrate.

Heterojunction photovoltaic device and fabrication method

A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and forming a continuous photovoltaic stack including an N-type layer, a P-type layer and an intrinsic layer on the first electrode. A second electrode layer is deposited over the photovoltaic stack such that gaps or fissures occur in the second electrode layer between the pillar structures. The second electrode layer is wet etched to open up the gaps or fissures and reduce the second electrode layer to form a three-dimensional electrode of substantially uniform thickness over the photovoltaic stack.

Three-dimensional conductive electrode for solar cell

A method of forming a semiconductor device that includes providing regions of epitaxial oxide material on a substrate of a first lattice dimension, wherein regions of the epitaxial oxide material separate regions of epitaxial semiconductor material having a second lattice dimension are different than the first lattice dimension to provide regions of strained semiconductor. The regions of the strained semiconductor material are patterned to provide regions of strained fin structures. The epitaxial oxide that is present in the gate cut space obstructs relaxation of the strained fin structures. A gate structure is formed on a channel region of the strained fin structures separating source and drain regions of the fin structures.

Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation

A semiconductor structure is provided in which a nanosheet device is formed laterally adjacent, but in proximity to, an embedded dynamic random access memory (eDRAM) cell. The eDRAM cell and the nanosheet device are connected by a doped polycrystalline semiconductor material that is formed during the epitaxial growth of doped single crystalline semiconductor source/drain regions of the nanosheet device. An eDRAM cut mask is used to remove unwanted semiconductor material from regions not including the eDRAM cell and the nanosheet device.

Nanosheet eDRAM

A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer.

Method of making a gallium nitride device

A photovoltaic device that includes an upper cell that absorbs a first range of wavelengths of light and a bottom cell that absorbs a second range of wavelengths of light. The bottom cell includes a heterojunction comprising a crystalline germanium containing (Ge) layer. At least one surface of the crystalline germanium (Ge) containing layer is in contact with a silicon (Si) containing layer having a larger band gap than the crystalline (Ge) containing layer.

Heterostructure germanium tandem junction solar cell

A photovoltaic device includes a substrate having a plurality of hole shapes formed therein. The plurality of hole shapes each have a hole opening extending from a first surface and narrowing with depth into the substrate. The plurality of hole shapes form a hole pattern on the first surface, and the hole pattern includes flat areas separating the hole shapes on the first surface. A photovoltaic device stack is formed on the first surface and extends into the hole shapes. Methods are also provided.

Cone-shaped holes for high efficiency thin film solar cells

Growing community of inventors

Hopewell Junction, NY, United States of America

Keith E Fogel