International Business Machines Corporation

Dongbu Electronics, Co. Ltd.

Keith E Barton

Yun-Yu Wang

John G Torok

Robert K Mullady

John J Loparco

John Gerard Gaudiello

John A Miller

Steven H Boettcher

George W Brehm

Stanley J Klepeis

Thomas A Bauer

Leon J Kimball

A high quality electron microscopy sample suitable for electron holography is prepared by forming markers filled with TEOS oxide and by repeatedly applying multiple coats of an adhesive followed by a relatively low temperature cure after each application. The TEOS oxide marker is readily visible during the polish, has a similar polish rate as a semiconductor material, and reduces contamination during sample preparation. The repeated application of adhesives separated by relatively low temperature cures increases the adhesive strength of the adhesive material to the semiconductor material without making it too brittle. This results in an improved control and yield of the sample preparation process.

Method of TEM sample preparation for electron holography for semiconductor devices

Methods of uniformly delayering an IC chip are disclosed. One embodiment includes: performing an ash on the wafer including an Al layer thereof and etching the Al layer; polishing an edge of the wafer using a slurry including an approximately 30 &#x3bc;m polishing particles; removing the aluminum layer and at least one metal layer by polishing using a slurry including approximately 9 &#x3bc;m diamond polishing particles and a non-abrasive backside of a polishing sheet; removing any remaining metal layers to a first metal layer by polishing using a slurry including approximately 3 &#x3bc;m diamond polishing particles and the non-abrasive backside of a polishing sheet; removing any scratches by polishing using a slurry including approximately 1 &#x3bc;m diamond polishing particles and the non-abrasive backside of a polishing sheet; and removing the first metal layer to a polyconductor layer by polishing using a colloidal slurry including approximately 0.25 &#x3bc;m diamond polishing particles.

IC chip uniform delayering methods

An aligning apparatus comprising: a back plane, the back plane comprising at least one back plane connector; at least one daughter card, the daughter card comprising: a lower edge, the lower edge comprising a scalloped surface proximal to a rear surface of the lower edge, and a ramped surface proximal to a front surface of the lower edge; and a daughter card connector, the daughter card connector configured to be removably connectable to the back plane connector; and at least two guide rails extending from the back plane, the guide rail comprising a rear ramp and a front ramp. A method of aligning a daughter card to a back plane, the method comprising: sliding the daughter card towards the back plane; lifting the front end of the daughter; lifting the back end of the daughter card after lifting the front end of the daughter card; and providing the back end of the daughter card with a degree of freedom to lift and lower in order to align to the back plane, after lifting the back end of the daughter card.

System and method for aligning and supporting interconnect systems

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Hyde Park, NY, United States of America

Keith E Barton