Globalfoundries U.S. Inc.

Globalfoundries Inc.

Keith Donegan

Yusheng Bian

Hsueh-Chung Chen

Martin O'Toole

Takako Hirokawa

Brendan O'Brien

Thomas Houghton

Julien Frougier

Terry Allen Spooner

Ming He

Craig Child

Nicholas LiCausi

Anbu Selvam Km Mahalingam

Colin Bombardier

Hyung Woo Kim

Steven M Shank

Qizhi Liu

Christopher J Penny

Louis DeWolf Lanzerotti

Nicholas A Polomoff

Somnath Ghosh

Ravi Prakash Srivastava

Robert Seidel

Atsushi Ogino

Torsten Huisinga

Vikrant Kumar Chauhan

Prakash Periasamy

Eswar Ramanathan

Sean Reidy

Qanit Takmeel

Ashwini Chandrashekar

Jeric Sarad

Adam L Da Silva

Jae O Choo

Carrie Yurkon

Kevin Dezfulian

Karen Nummy

Structures including a cavity adjacent to an edge coupler and methods of forming such structures. The structure comprises a semiconductor substrate including a cavity with a sidewall, a dielectric layer on the semiconductor substrate, and an edge coupler on the dielectric layer. The structure further comprises a fill region including a plurality of fill features adjacent to the edge coupler. The fill region includes a reference marker at least partially surrounded by the plurality of fill features, and the reference marker has a perimeter that surrounds a surface area of the dielectric layer, and the surface area overlaps with a portion of the sidewall of the cavity.

Reference markers adjacent to a cavity in a photonics chip

IC chips for photonics applications are disclosed. An example IC chip includes a substrate, an optical component above the substrate, and a first connection level above the substrate. The first connection level includes the optical component and a first cladding structure, in which the optical component is covered by the first cladding structure. The IC chip also includes a second connection level on the first connection level. The second connection level includes a first interlayer dielectric material. The IC chip further includes a second cladding structure directly above the optical component. The second cladding structure has at least a section within the second connection level. The second cladding structure is on the first cladding structure. The second cladding structure is laterally adjacent to and in direct contact with the first interlayer dielectric material. The second cladding structure includes a material different from the first interlayer dielectric material.

Cladding structure in the back end of line of photonics chips

Structures including a calibration marker adjacent to a photonic structure and methods of forming such structures. The structure comprises a semiconductor substrate, a photonic structure, and a back-end-of-line stack over the semiconductor substrate. The back-end-of-line stack includes a plurality of fill features, an exclusion area surrounded by the plurality of fill features, and a calibration marker in the exclusion area. The calibration marker is disposed adjacent to the photonic structure, and the calibration marker includes a feature having a predetermined dimension.

Calibration markers for a photonics chip

Structures including an edge coupler, and methods of fabricating a structure that includes an edge coupler. The structure includes an edge coupler having a waveguide core with an end surface and a longitudinal axis. The end surface defines a plane tilted in a first direction at a first acute angle relative to the longitudinal axis and tilted in a second direction at a second acute angle relative to the longitudinal axis. The second direction differs from the first direction.

Spot-size converters with angled facets

Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.

Multiple patterning with mandrel cuts defined by block masks

One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

Methods of forming a conductive contact structure to an embedded memory device on an IC product and a corresponding IC product

One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.

Methods of self-aligned multiple patterning. A mandrel is formed over a hardmask, and a planarizing layer is formed over the mandrel and the hardmask. The planarizing layer is patterned to form first and second trenches exposing respective first and second lengthwise sections of the mandrel. A portion of the patterned planarizing layer covers a third lengthwise section of the mandrel arranged between the first and second lengthwise sections of the mandrel. After patterning the planarizing layer, the first and second lengthwise sections of the mandrel are removed with an etching process to define a pattern including a mandrel line exposing respective first portions of the hardmask. The third lengthwise section of the mandrel is masked by the portion of the planarizing layer during the etching process, and the third lengthwise section covers a second portion of the hardmask arranged along the mandrel line between the first portions of the hardmask.

Multiple patterning with late lithographically-defined mandrel cuts

Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

Interconnect formation with chamferless via, and related interconnect

Embodiments of the disclosure provide a substrate structure for an integrated circuit (IC) structure, including: a first dielectric layer positioned above a semiconductor substrate; a first plurality of trenches extending at least partially into the first dielectric layer from an upper surface of the first dielectric layer; and a first metal formed within the first plurality of trenches, wherein a spatial arrangement of the first plurality of trenches causes coupling of surface plasmons in the first metal to at least one wavelength of an incident light.

Substrate structure with spatial arrangement configured for coupling of surface plasmons to incident light

Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.

Multi-directional self-aligned multiple patterning

One method disclosed herein includes forming a layer of insulating material above a semiconductor substrate, forming a hard mask layer comprised of a metal-containing material above the layer of insulating material, forming a blanket protection layer on the hard mask layer, forming a masking layer above the protection layer, performing at least one etching process on the masking layer to form a patterned masking layer having an opening that stops on and exposes a portion of the blanket protection layer, confirming that the patterned masking layer is properly positioned relative to at least one underlying structure or layer and, after confirming that the patterned masking layer is properly positioned, performing at least one etching process through the patterned masking layer to pattern at least the blanket protection layer.

Methods of forming a protection layer to protect a metal hard mask layer during lithography reworking processes

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Saratoga Springs, NY, United States of America

Keith Donegan