Texas Instruments Corporation

Other

Keith Balmer

Karl M Guttag

Robert J Gove

Nicholas K Ing-Simmons

Christopher Jensen Read

Sydney W Poland

Jeremiah E Golston

Iain Craig Robertson

Philip John Moyse

David J Hoyle

John D Keay

Amarjit Singh Bhandal

Phillip Moyse

Gary L Swoboda

Richard D Simpson

Lewis Nardini

Douglas E Deao

Mark R Hammes

Nick Ing-Simmons

Charles Lance Fuoco

Sanjive Agarwala

Andre Szczepanek

David A Comisky

Zahid Hussain

Denis Roland Beaudoin

Christopher L Mobley

Nicholas Ing Simmons

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

Long instruction word controlling plural independent processor operations

A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.

Transfer request bus node for transfer controller with hub and ports

A method for processing data using a multiplexing architecture includes performing a selected one of a plurality of first multiplexer operations on the data and then a selected one of a plurality of second multiplexer operations. The first multiplexer operations include a pass operation and a plurality of bit rearrangement operations. The second multiplexer operations include a pass operation and a plurality of bit duplication operations which duplicates a selected bit or bits to a corresponding block of contiguous bits in the output. A result is then generated that reflects the outputs produced by first and second multiplexers respectively.

System and method for using a two-stage multiplexing architecture for performing combinations of passing, rearranging, and duplicating operations on data

A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware

A data processing apparatus includes first () and second () functional unit groups, each includes a plurality of functional units and a register file () comprising a plurality of registers. A comparator () receives the operand register number of a current instruction for a functional unit in the first functional unit group, and the destination register number of an immediately preceding instruction for the second functional unit group. A register file bypass multiplexer () selects the data from the register corresponding to the operand number of the current instruction on no match and selects the output of the second functional unit group (hotpath) if the comparator indicates a match. The first functional unit utilizes the output of the second functional unit group without waiting for the result to be stored in the register file.

Data processing apparatus with register file bypass

A data processing system (e.g., microprocessor ) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory ( ) and a central processing unit core ( ) with at least one register file ( ). The core is responsive to a load instruction (e.g., LDW_BH&lsqb;U&rsqb; instruction ) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction ) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data. A single store or load instruction can perform all of the tasks that used to take several instructions, while at the same time conserving memory space.

Data processing system with register store/load utilizing data packing/unpacking

The method maps at least one intermediate data register of a first data width into the address space of the computer bus. The computer bus writes data to an intermediate data registers with write strobes corresponding to data subsets of a second smaller data width equal to the data width of the device registers. The IDE controller then transfers data from the intermediate data register to the device registers in subsets of the device register data width in a fixed order of device registers. Similarly, for reads of the device register, the computer bus writes data to a read selection data field of an intermediate data register. Each bit of the read selection data field corresponding to one device register. The IDE controller transfers data from the device registers corresponding to bits of the read selection data field having a predetermined first digital state to an intermediate data register in a fixed read order of device registers.

Batch method for accessing IDE device task registers

A data processing apparatus which uses a register file to provide a faster alternative to indirect memory addressing. A functional unit is connected to a data register file ( ) which comprises a plurality of registers, each of which is accessed by a corresponding register number. The functional unit (e.g., A-unit ) can execute at least one indirect register access instruction that comprises an operand register number field. Instruction decode circuitry, connected to the register file and the functional unit, is responsive to the indirect register access instruction to recall data stored in an operand register ( ) specified by the operand register number in the instruction, identify the recalled data as a register access number, and recall operand data from a data register corresponding to the register access number for use as an operand by the functional unit. Indirect register addressing permits the apparatus to more quickly execute table look up intensive algorithms, such as variable length decoding, than an apparatus employing only indirect memory addressing.

Data processing apparatus with indirect register file access

A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand ( ) and storing the shuffled result in a selected destination register ( ). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.

Microprocessor with instructions for shuffling and dealing data

An embodiment of the invention includes a pair of parallel 16&times;16 multipliers each with two 32-bit inputs and one 32-bit output. There are options to allow input halfword and byte selection for four independent 8&times;8 or two independent 16&times;16 multiplications, real and imaginary parts of comple&times;multiplication, pairs of partial sums for 32&times;32 multiplication, and partial sums for 16&times;32 multiplication. There are options to allow internal hardwired routing of each multiplier unit results to achieve partial-sum shifting as required to support above options. There is a redundant digit arithmetic adder before final outputs to support additions for partial sum accumulation, complex multiplication vector accumulation and general accumulation for FIRs/IIRs&mdash;giving MAC unit functionality. There are options controlled using bit fields in a control register passed to the multiplier unit as an operand. There are also options to generate all of the products needed for complex multiplication.

Data processor with flexible multiply unit

Data transfer between a master node ( ) and plural memory nodes ( ) follows a synchronous fixed latency loop bus ( ). Each memory node includes bus interface ( ) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.

Method and apparatus for data transfer employing closed loop of memory nodes

Data transfer between multiple processor nodes and multiple static memory storage nodes is made more efficient using a wrapper of logic surrounding a conventional single port static memory function. The wrapper logic comprises FIFO devices which provide buffering between a given processor node and its associated memory function. The added buffering allows the design to trade allowable added read and write latency for a significant reduction in memory complexity. A single port random access memory structure enclosed within the wrapper provides the functional throughput advantage that only a dual port memory device would otherwise make possible.

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Bedford, United Kingdom

Keith Balmer