Ncr Corporation

Hyundai Electronics America, Inc.

At&t Global Information Solutions Company

Symbios Logic Inc.

Lsi Logic Corporation

Symbios, Inc.

Maryland

Keith B DuLac

Bret S Weber

Dennis E Gates

Robert A DeMoss

Paul M Freeman

William V Courtright, Ii

Grover G Phillips

T M Ravi

An apparatus for storing and playing videos. The apparatus includes a storage device containing a video for playback on a user system located on a communications network. The apparatus includes a system connection to a data processing system and a network connection to the communications network. The apparatus includes a transfer means for transferring the video from the storage device to the network using the network connection, wherein the video is directly transferred from the apparatus to the network.

Video storage unit architecture

A bus switch providing versatile data path routing between a first group of busses associated with a disk array controller and a second group of busses associated with the individual disk drives within the disk array. The bus switch comprises a plurality of bus multiplexers, equal in number to the number of drive busses. Each bus multiplexer includes a plurality of inputs, each input being connected to a corresponding one of the controller busses. The multiplexers are responsive to select and enable signals to connect selected controller busses to selected drive busses. The bus switch additionally includes a plurality of bus multiplexers for directing data from the drive busses to the controller busses. A parity generator comprising an exclusive-OR circuit is integrated with the bus switch. The output of the parity generator is also provided to each of the multiplexers and can be directed thereby to any of the controller or drive busses.

Multiple channel data bus routing switching including parity generation

A digital video storage system, suitable for use within a movie-on-demand (MOD) system, includes a plurality of disk drive storage devices; the disk drives being connected together serially to form a loop, wherein each disk drive within the loop has an input for receiving digital video data for storage and an output for providing stored digital video data, the output of each disk drive being connected to the input of the succeeding disk drive in the loop. Successive segments of a video program, stored on successive disk drives in the loop, are each repeatedly moved at a predefined time interval from the disk drive on which the segments are currently stored to the succeeding disk drive in the loop. A plurality of taps are connected to the loop to provide connection points for MOD subscribers or viewers for receiving the video program from the loop. Each tap corresponds to the output of one of the plurality of disk drives. During operation, the video program is provided at each tap, however at any instant each tap is providing a different segment of the video program. The system also includes means for changing the tap to which a MOD subscriber or viewer is connected in response to a request received from the viewer. This feature allows the MOD subscriber to pause, play, or to jump forward or backward in time to the beginning of any movie segment, simulating the operation of a VCR or video disk player.

Movie-on-demand disk storage loop architecture

An apparatus includes a first bus, a second bus, and a storage module having a first and second output with the first output being connected to the first bus and a second output being connected to the second bus. A first buffer storage and a second buffer storage in which the first buffer storage is connected to the first bus and the second buffer storage is connected to the second bus. The second buffer storage includes an error correction module. First and second network adapters are connected to the first and second buses respectively. The first network adapter also includes a connection to the first buffer. A processor in the apparatus includes a first processor circuitry for transferring the data using a first path through the first output in the storage module to the first buffer storage and from the first buffer storage to the first network adapter. A second processor circuitry is for transferring data using a second path through the second output to the second buffer storage through the error correction module and from the second buffer storage to the second network adapter, wherein the second processor circuitry is responsive to an error in the storage module.

Dual bus architecture for a storage device

A Video-On-Demand (VOD) system including a plurality of video storage devices; an asynchronous transfer mode (ATM) telephony technology network connected to provide video data to a plurality of subscribers; and a unique video server coordinating the conversion and transfer of video data from computer technology devices to the ATM telephony technology network. The video server includes a data converter for converting a first video data stream transmitted via computer technology, fiber channel links, to a second video data stream for transmission via said ATM telephony technology network; a multi-port switch connected to receive said first video data stream from one of a plurality of video data storage devices, such as disk array or tape storage devices, and connected to provide said first video data stream to said data converter; and a controller connected to receive a viewer request signal from a subscriber via said telephony technology network and responsive thereto to generate and provide control signals to said multi-port switch and said data converter for coordinating the transfer video data streams from said video data storage devices to said telephony technology network.

Architectural arrangement for a video server

A data storage system comprising a matrix of intelligent storage nodes interconnected to communicate with each other via a network of busses. The network of busses includes a plurality of first busses for conducting data from and to a corresponding plurality of host system processors and a plurality of second busses, each one of the second busses intersecting with each one of the first busses. The nodes are located at each intersection. The storage nodes each include a data storage device, such as a magnetic disk drive unit, a processor and buffer memory, whereby the node processor controls the storage and retrieval of data at the node as well as being capable of coordinating the storage and retrieval of data at other nodes within the network.

Data storage device matrix architecture

A method for reducing the apparent response time for write I/O operations initiated by a host system to a RAID level 3, 4 or 5 disk array including a spare disk drive. The disclosed method comprises the steps of (1) saving write data received by the disk array from the host system directly to the spare drive, (2) issuing a write complete status signal to the host system indicating completion of the host write I/O operation, thus freeing the host processor to perform other functions, and (3) transferring the data saved to the spare drive to the active drives within the array. This third step may be executed at any convenient time following the second step. For example, in systems where a host processor functions as the array controller, this third step may be delayed while higher priority tasks are executed. In systems where the disk array includes an array controller, the array controller coordinates the execution of this third step with other controller or array operations to optimize array operation. In additiona, the data from multiple write I/O opertions may be accumulated to the spare drive prior to the step of transferring the data saved to the spare drive to the other, active, drives within the array.

Fast write I/O handling in a disk array using spare drive for buffering

An improved method for updating data and parity information in a RAID level 4 or 5 disk array employing a read-modify-write (RMW) process for updating data and parity information. During normal RMW operations, the old data and old parity information to be updated are read from disk, new parity is generated, and the new parity information and new data written to disk. The improved RMW method separates the execution of data read and write operations from the execution of parity read, generation and write operations to permit greater efficiency in the utilization of the drives within the array. The method identifies the disk drives containing the data and parity to be updated and places the proper read and write requests into the I/O queues for the identified data and parity drives, scheduling parity operations; i.e. reading old parity information from the parity drive, generating new parity information and writing the new parity information to the parity drive; for execution when best accommodated in the I/O queue for the parity drive, following the read of old data from the data drive.

Delayed initiation of read-modify-write parity operations in a raid

A disk array controller providing a variable configuration data path between the host system and the individual disk drives within a disk array and parity and error correcting code generation and checking. The controller includes host interface logic for converting data received from the host system via a 16 or 32-bit SCSI bus to 16, 32 or 64-bit data words multiplexed across one, two or four 16-bit buffer busses, and for converting data received from the buffer busses to the proper form for transmission to the host system. A bus switch, including an exclusive-OR circuit for generating parity information, is connected between the buffer busses and six disk drive busses for directing the transfer of data and parity information between selected buffer and drive busses. The controller further includes a storage buffer connected to the buffer busses to provide temporary storage of data and parity information. The host interface logic, bus switch and storage buffer, under the direction of an included processor and DMA control logic, performs array read and write operations requested by the host system in accordance with RAID level 1, 3, 4 or 5 protocols.

Disk controller having host interface and bus switches for selecting

The present invention couples a disk drive to a small computer system interface bus by means of two buffers connected between a buffer-in bus and a buffer-out bus to allow data to be read out from a first filled buffer onto the buffer-out bus, while simultaneously permitting a filling of the second buffer from the buffer-in bus. When the second buffer is full and the first buffer is empty, the second buffer may be read while the first buffer is again filled. Toggling between the two buffers continues until the required data transfer is complete.

Integrated controller using alternately filled and emptied buffers for

A SCSI disk controller integrated circuit (SDC IC) provides much of the hardware necessary to perform asynchronous data transfers between a SCSI host bus and a disk interface circuit through two on-chip rotating buffers. The SDC IC is designed to be used in conjunction with a microprocessor and a stored microprocessor program. The SDC IC with its numerous registers reduce external parts by allowing some of the SCSI disk controller functions to be performed in software rather than hardware. On-chip sequence controllers and the rotating buffers of the SDC IC help the microprocessor to separate the control functions and the data transfer functions in order to maximize data transfer throughput. By arranging the control registers, the rotating buffers, and the sequence controller on a single integrated circuit a high performance, compact and inexpensive disk controller can be built using the SDC IC, a microprocessor and a small number of additional integrated circuits.

Architectural arrangement for a SCSI disk controller integrated circuit

A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.

Multiple port bus interface controller with slave bus

A compact register file circuit, especially valuable for CMOS VLSI circuits used with microcontrollers, which uses a pseudo static random access memory array circuit, a latch array circuit, and a decoder circuit to provide almost identical characteristics as available with a much larger static random access memory as a register set. The only differences visible to the user during a read operation is the requirement of keeping the address data value constant during the active portion of the pseudo static random access memory chip select waveform.

Compact register set using a psram array

A disk drive controller bus architecture for interfacing disk drives having widely varying data format requirements with small computer systems is comprised of a disk drive parameter storage section, a disk drive parameter compartor/interface section and a set of associated data buses, coupled between a disk drive controller processor and the disk drive. The disk drive parameter storage section contains a set of control registers and a (format option) random access memory which may be written to and read by the control processor and serves to store drive control codes that are selectively coupled over a first of the set of associated data buses for application to the disk drive parameter comparator/interface section. The disk drive parameter comparator/interface section contains multiplexer and format conversion circuitry for interfacing data between the disk, storage/buffer components of the bus architecture itself, and the control processor. This section also contains comparator and auxiliary storage circuitry coupled with a second of the set of associated data buses, for comparing data read from the disk with parameter data stored in and selectively accessed from the disk drive parameter storage section.

Growing community of inventors

Derby, KS, United States of America

Keith B DuLac