Analog Devices Global

Cypress Semiconductor Corporation

Qualcomm Incorporated

Analog Devices International Unlimited Company

Keith Anthony O'Donoghue

Paul M Walsh

Hongxing Li

Niall Kevin Kearney

Hans Klein

Roman Ogirko

Abhishek Bandyopadhyay

Akira Shikata

Baptiste Grave

A system includes a bandgap voltage generator coupled to a voltage supply and configured to produce a plurality of reference voltage levels in response to a plurality of calibration codes; an analog-to-digital converter (ADC) coupled to a reference voltage output of the bandgap voltage generator; a logic circuit coupled to an output of the ADC; a first memory element coupled to the logic circuit and configured to store a calibration coefficient indicative of a relationship of the calibration codes and the reference voltage levels; and a second memory element coupled to the logic circuit and configured to store a value of a first reference voltage level for the reference voltage output, wherein the logic circuit is configured to generate a first calibration code from the value of the first reference voltage level and the calibration coefficient.

Circuits and methods providing bandgap calibration

Methods and devices are described for controlling excess loop delay (ELD) gain compensation in a digital-to-analog converter (DAC) of a successive approximation register (SAR) analog-to-digital converter (ADC) by using DAC unit elements in the ELD DAC and DACs for the SAR ADC efficiently. The ELD DAC and DAC partially share DAC units (e.g. capacitors or current sources) to minimize total DAC units used to limit area and power usage while maintaining operational flexibility. Different configurations provide ELD gains of less than or greater than one. A dedicated sampling capacitor is also provided to allow flexible gain control by capacitance ratio.

Method to embed ELD DAC in SAR quantizer

A latency associated with a receiver circuit, e.g., radio receiver circuit, can be reduced by applying digital data from an analog signal received by a receiver, e.g., a radio receiver, to an automatic gain control circuit without first using a decimation and digital filtering process, which can minimize or eliminate significant latency associated with the decimation and filtering process.

Dual-input analog-to-digital converter for improved receiver gain control

A dynamically tunable transconductor includes a voltage-to-current converter stage for generating a current signal based on a voltage signal; and a current scaling stage for scaling the current signal by a scaling factor to achieve a particular transconductance. Current scaling stage includes a coarse tune mechanism having an associated coarse tune step and a fine tune mechanism having an associated fine tune step, where the scaling factor is a ratio of the coarse tune step to the fine tune step. A delta-sigma modulator can implement the transconductor to generate loop filter coefficients by dynamically tuning the transconductance to achieve a particular resistance.

Delta-sigma modulator having transconductor network for dynamically tuning loop filter coefficients

An analog to digital convertor (ADC) comprises an integrator having an input selectively connected to an intermediate frequency (IF) signal input and an output connected to a summer. The summer has an output connected to an input of a quantizer, the quantizer output being operatively connected to a signal strength indicator. The integrator includes a programmable gain feedback component. The summer has a synthesized calibration signal input, the value of the programmable gain feedback component being configured to vary when a synthesized calibration signal at the intermediate frequency is applied to the summer. The signal strength indicator is configured to detect a value of the programmable gain feedback component when the signal strength is minimized and to calibrate the ADC accordingly.

Analog to digital convertor and a method of calibrating same

A compensation circuit may include a current source configured to control an amplitude of a current pulse, a memory configured to store a plurality of duration values each corresponding to a set of one or more sensor electrodes of a plurality of sensor electrodes, and a pulse width controller configured to control a duration of the current pulse based on a first duration value of the plurality of duration values, and to apply the current pulse to a compensation node of a capacitance sensor during a measurement cycle for a first set of one or more sensor electrodes, where the first set of one or more sensor electrodes corresponds to the first duration value.

Baseline charge compensation

Apparatuses and methods of an integrated capacitance model circuit are described. A capacitance model circuit is disposed on a common carrier substrate of an integrated circuit (IC) having a capacitance-sensing device. The capacitance model circuit is configured to model a capacitance of an external sense array. The capacitance model circuit is programmable.

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Cork, Ireland

Keith Anthony O'Donoghue