Motorola Corporation

Motorola Mobility LLC

Keith Andrew Tilley

Raul Salvi

Enrique Ferrer

Walter H Kehler

David J Graham

Rajesh H Zele

Peter Nanni

Greg R Black

Thomas D Nagode

Dane E Blackburn

Louis M Nigra

Atif A Meraj

James C Goatley

A transmitter circuit () and method reduces amplitude modulation distortion in an amplifier (). The transmitter circuit () includes a power control error data generator (), a feedforward predistortion data generator (), feedforward adder logic () and the amplifier (). The power control error data generator () receives amplitude modulation data () and an RF coupled output signal () and, in response, produces power control error data (). The feedforward predistortion data generator () receives the amplitude modulation data () and, in response, produces feedforward predistortion data (). The feedforward adder logic () receives the power control error data () and the feedforward predistortion data () and, in response, produces power control data (). The amplifier () receives the power control data () and an RF input signal () and, in response, produces an RF output signal (), such that the power control data () reduces amplitude modulation distortion in the RF output signal ().

Transmitter circuit and method for modulation distortion compensation

A DC offset correction method and apparatus. In a differential system, a DC offset correction loop includes a gain stage ( ) having a differential input, a gain G and a differential output. A DAC circuit ( ) provides a correction DC signal at the inputs to produce differential output signals V &prime; and {overscore (V )}&prime;. A controller ( ) corrects the DC offset by stepping the DAC circuit ( ) to change the correction DC signal by an amount equal to approximately (V &prime;&minus;{overscore (V &prime;)})/G , where G is the gain G times the gain of the DAC expressed in volts per DAC step. A similar algorithm can be applied to single ended systems wherein a single ended V is corrected by an amount equal to approximately V /G .

Smart DC offset correction loop

A receiver includes a main loop ( ) having a main VCO ( ) and a secondary loop ( ) having a secondary VCO ( ). The receiver momentarily phase locks an incoming RF signal ( ), and then samples and stores a correction voltage ( ) being applied to the main VCO ( ). The main loop ( ) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit ( ) to the main VCO ( ) for the duration of the incoming RF signal ( ). This effectively calibrates the LO frequency ( ) of the receiver to the incoming RF signal frequency ( ).

Method and apparatus for calibrating a local oscillator in a direct conversion receiver

A DC offset correction method and apparatus. In a DC offset correction loop ( ), a DC offset is corrected using a binary search routine or any other digital or analog DC offset correction technique. In this binary search routine, the sign of the offset ( ) is used to control a direction in which a digital to analog converter (DAC) ( ) is stepped until the least significant bit of the DAC is set. The process is enhanced by opening up the bandwidth of the baseband filters ( ) to permit the binary search to be clocked ( ) at a higher clock rate. After the correction is established, the filters ( ) are reset to normal operating conditions.

Enhanced DC offset correction through bandwidth and clock speed selection

A multimode fast attack automatic gain control (AGC) circuit (,) includes an analog feedback loop and a digital feedback loop. The analog feedback loop is switched into the amplifier stage (,) by a first switch (,) when dynamic control of the gain attenuation is desired. The digital feedback loop is switched into the amplifier stage when attenuation is to be adjusted periodically, such as between sequentially received time slots in a time division multiple access (TDMA) mode of communication.

Multimode fast attack automatic gain control (AGC) loop for narrow band receivers

A DC offset correction method and apparatus. Several DC offset correction schemes including a digital binary search scheme (,), a digital slow averaging scheme (,) and an analog integration (,) scheme are provided. A controller (,) selects one or more of the correction schemes in accordance with the desired characteristics provided by each scheme.

DC offset correction adaptable to multiple requirements

A DC offset correction loop (,) utilizes a sign bit generator (,), binary search stage (,), and a digital-to-analog converter (,) in its feedback path to correct for DC offsets at the input of a gain stage (,). When a correction value is obtained, it is applied and held (,) to compensate for the DC offset. When a programming event occurs (,), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.

Method and apparatus for settling and maintaining a DC offset

A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Method and apparatus for calibrating a local oscillator in a direct

A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202).

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Round Rock, TX, United States of America

Keith Andrew Tilley