Advanced Micro Devices Corporation

Keith Allen Kasprak

Russell J Schreiber

John J Wuu

Amlan Ghosh

James A Wingfield

Michael Estlick

Michael L Golden

Martin Paul Piorkowski

Donald A Priore

Eric W Busta

Tawfik Ahmed

Arijit Banerjee

William A Halliday

Srinivas R Sathu

Ricardo Cantu

Sean M O′Mullan

John Reginald Riley, Iii

Patrick W Shaw

Vance Threatt

A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

SRAM power savings and write assist

An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

Methods and apparatus for managing register free lists

An integrated circuit includes a memory core and a built-in self-test (BIST) controller. The memory core has an array of memory cells located at intersections of a plurality of word lines and a plurality of bit line pairs. The BIST controller is coupled to the memory core and has a mission mode and a built-in self-test mode. When in the mission mode, the BIST controller performs read and write accesses using precharge on demand. When in the built-in self-test mode, the BIST controller performs a floating bit line test by draining a voltage on true and complement bit lines of a selected bit line pair and subsequently precharging the true and complement bit lines of the selected bit line pair, before reading or writing data using the true and complement bit lines of the selected bit line pair.

Integrated circuit memory with built-in self-test (BIST)

A circuit includes a repeating series of first circuits and a repeating series of second circuits placed next to the repeating series of first circuits and interacts with corresponding portions of the first circuits in the series. The repeating series of second circuits is formed in diffusion regions and diffusion wells which extend along the direction in which the second circuits repeat. The repeating series of the first and second circuits is interrupted by at least one dummy circuit region, which occupies the space of one or more instances of the first and second repeating series. The dummy circuit region also includes taps for biasing the diffusion regions and diffusion wells of the second circuits.

Nwell and subtrate taps in memory layout

Systems, apparatuses, and methods for efficiently floor planning a semiconductor chip are disclosed. Within either the processor or the memory of a computing system, each of a first block and a neighboring second block has a same height. A first metal track plan for the first block is unaligned with respect to a second metal track plan for the second block. An offset for moving each track of the second metal plan to align with a track of the first metal track plan is determined where the offset is a fraction of the height. The placement of the second block is shifted by the offset with respect to the first block. The shifted placement of the second block allows the first metal track plan for the first block to use a unidirectional pattern across the first block and the second block.

Shift of circuit periphery layout to leverage optimal use of available metal tracks in periphery logic

Write assist circuitry facilitates increased voltage applied to a memory device such as a memory cell or bitcell in changing a logical state of the memory device during a write operation. The write assist circuitry includes a second capacitive line or 'metal cap' in addition to a first capacitive line coupled to one of a pair of bitlines to which voltage may be selectively applied. The capacitive lines provide increased write assistance to the memory device. The second capacitive line structurally lies in a second orientation and is formed in an integrated circuit second metal layer relative to the first capacitive line in some embodiments. The additional capacitive line provides negative bitline assistance by selectively driving its corresponding bitlines to be negative during a write operation.

Capacitive structure for memory write assist

A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.

VSS bitcell sleep scheme involving modified bitcell for terminating sleep regions

A test circuit for a static random access memory (SRAM) array includes a plurality of stages coupled in a ring. Each stage includes a plurality of bit cells to store information, a bit line and a complementary bit line coupled to the plurality of bit cells, and a plurality of word lines coupled to the plurality of bit cells. Subsets of the plurality of word lines of each of the plurality of stages are selectively enabled based on signals asserted on the complementary bit line of another one of the plurality of stages. The test circuit also includes inversion logic deployed between two of the plurality of stages.

Memory array test logic

An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

Voltage-aware signal path synchronization

An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.

Memory cell flipping for mitigating SRAM BTI

A sense amplifier circuit is provided with a first transistor arrangement comprising a first n-type field effect transistor (NFET) having a respective body node, and a second transistor arrangement comprising a second NFET having a respective body node. The second transistor arrangement is electrically coupled to the first transistor arrangement, and the body node of the first NFET is electrically coupled to the body node of the second NFET. The sense amplifier circuit also includes or cooperates with a voltage condition selector that is electrically coupled to the body node of the first NFET and to the body node of the second NFET. The voltage condition selector is configured to assert one of a plurality of voltage conditions at the body node of the first NFET and at the body node of the second NFET.

Sense amplifier circuit and related configuration and operation methods

A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor.

Memory device and methods thereof

A memory device is disclosed that includes a plurality of word-lines, with each word-line connected to at least one bitcell. Each of the plurality of word-lines is connected to a corresponding driver module to drive the word-line in response to a corresponding select signal. Further, each driver module is connected to a level shifter to shift the corresponding select signal so that the driver module provides a level-shifted signal at the first word-line in response to assertion of the first select signal. A single level shifter can be connected to multiple driver modules, thereby reducing the area required to implement level-shifting for multiple word-lines.

Voltage shifting word-line driver and method therefor

A method of simulating operation of a bitcell includes determining sensitivities of a bitcell model to different component characteristics and device parameters, such as device temperature, operating voltage, and process characteristics. The determined sensitivities are normalized, so that each normalized value represents the relative sensitivity of the bitcell, under the simulated device parameters, to the component characteristic associated with the value. The normalized sensitivity values can be scaled based on a tolerance factor, and the adjusted sensitivities used to model the behavior of each component of the bitcell in subsequent simulations.

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Austin, TX, United States of America

Keith Allen Kasprak