Apple Inc.

International Business Machines Corporation

Keith Alan Cox

Michael F Culbert

David Gerard Conroy

James S Ismail

Gaurav Kapoor

Inder M Sodhi

John Gregory Dorsey

Patrick Y Law

Josh P De Cesare

Norman Jay Rohrer

John Meron Ananny

Robert A Drebin

Brian D Howard

Richard Charles Williams

Dave Robbins Falkenburg

Daisie Iris Huang

Victor Zyuban

Amaury J Heresztyn

Joshua P De Cesare

Gerard Richard Williams

Achmed Rumi Zahir

Frank Faqiu Liang

Joseph T DiBene, Ii

Doron Rajwan

William C Athas

Cyril De La Cropte De Chanterac

Kenneth Christian Dyke

Tal Kuzi

Jamie L Langlinais

Nagarajan Kalyanasundaram

Dave Radcliffe

David Radcliffe

Eric Steven Jol

Jeffrey J Terlizzi

Albert John Golko

Manu Gulati

Donald Joseph Novotney

Marc Albrecht

Parin Patel

Todd K Moyer

Jung Wook Cho

Kit-Man Wan

Vaughn Todd Arnold

Steven G Herbst

Jeffrey M Alves

Guy G Sotomayor

Antonietta Oliva

Eric J Albert

Matthew G Watson

Jim C Hwang

Alex J Crumlin

Jan Krellner

Andrew Bradley Just

Robert S Parnell

Derek J DiCarlo

Jason Luo Pang

Stephen D Sterz

Ron Neuman

David Matthew Powers

Daniel Ariel West

Daniele Perretta

Kevin I Park

Carmel Yamberger

Timothy John Millet

Gabriel G Marcu

Erik P Machnicki

Hugo Fiennes

Sandro Hermann Pintz

Christopher P Tann

John Mathew Depew

Lior Zimet

Nathaniel C Begeman

Jay S Nigen

Ulrich Tobias Barnhoefer

Bryan R Hinch

Ihtesham H Chowdhury

Andrei Dorofeev

Thoi Nguyen

Jerry Hauck

Michael Eng

Sribalan Santhanam

Yizhang Yang

Christopher J Young

Richard Nicholas Iachetta, Jr

Aditya Venkataraman

Derek Fujio Iwamoto

Ashish R Jain

Ching Elizabeth Ho

Reza Arastoo

Russell Dean Reece

Sung Wook Kang

Allan Rowe Steel

Jeffrey D Whitman

Mike Culbert

Diwakar N Tundlam

Douglas A MacKay

Yashwant Sakarchand Kothari

Mohamed H Abu-Rama

Karl D Vulkan

Eric Albert

Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.

PMU-side electromigration control

In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Systems and methods for coherent power management

In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.

Power management for a graphics processing unit or other circuit

A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.

Scalable, hierarchical power delivery system

In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Request and floor interface for current control with correctness in an SOC

Global integrated circuit power control

Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.

Power delivery reduction scheme for SoC

Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.

PMU-side thermal control

A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.

Temperature control loop for integrated circuit

A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

Adaptive memory performance control by thread group

Systems and methods are disclosed for allocating and distributing power management budgets for subsystems (e.g., power usage clients) of a computer system. A power budget allocation subsystem may include a plurality of feedback branches having different associated time constants. Power usage clients with slower power response times may be provided power budgets based on a feedback branch having an associated longer time constant, while power usage clients with faster power response times may be provided with power budgets based on a feedback branch having an associated shorter time constant. The power budgets may be determined in the feedback branches based on power budgeting policies weighting the power budget of each subsystem relative to total power mitigation.

Coherent power management system for managing clients of varying power usage adaptability

In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

Method for multiplexing between power supply signals for voltage limited circuits

Growing community of inventors

Campbell, CA, United States of America

Keith Alan Cox