International Business Machines Corporation

Keith Aelwyn Jenkins

Barry P Linder

Peilin Song

Kevin Geoffrey Stawiasz

Karthik Balakrishnan

Shu-Jen Han

Franco Stellari

Robert Louis Franch

Jae-Joon Kim

Raphael Peter Robertazzi

James H Stathis

Scott Kevin Reynolds

Chen-Yong Cher

Yu-Ming Lin

Emmanuel Yashchin

Alan Weger

Rahul M Rao

Emily A Ray

Anup Paul Jose

Supratik Guha

Wilfried Haensch

Dirk Pfeiffer

Tymon Barwicz

Seongwon Kim

Mehmet Soyuer

Christos Vezyrtzis

Joachim Norbert Burghartz

David F Heidel

Anuja Sehgal

Daniel C Edelstein

Guy M Cohen

Alberto Valdes Garcia

Stephen Victor Kosonocky

Bruce Martin Fleischer

Stanislav Polonsky

Chirag Suryakant Patel

Pascal A Nsame

Alberto Valdes-Garcia

Mounir Meghelli

Manjul Bhushan

Siyuranga O Koswatta

Carole D Graas

Aditya Bansal

Kai Zhao

Saila Ponnapalli

James Patrick Eckhardt

Tian Xia

Emmanuel F Crabbe

Tam N Huynh

Pierce I Chuang

Jien-Chung Lo

Lie Shan

Jeffrey L Snare

A computer system may determine a first set of output values for a set of test paths at a first time. Each output value may correspond to a test path in the set of test paths. The computer system may then determine a second set of output values at a second time. Each output value in the second set of output values may have an associated output value in the first set of output values. The computer system may then determine whether degradation of the semiconductor chip has occurred by comparing the first set of output values to the second set of output values.

Degradation monitoring of semiconductor chips

Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

Detection of performance degradation in integrated circuits

Methods and systems for measuring degradation includes measuring an initial electrical characteristic of a test device in a ring oscillator that includes multiple oscillator stages and a test stage having a delay stage and the test device. The ring oscillator is operated for a period of time. The electrical characteristic of the test device is measured after operating the ring oscillator. A level of degradation in the test device is determined using a processor based on the measurements of the electrical characteristic of the test device.

Measuring individual device degradation in CMOS circuits

Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

BTI degradation test circuit

A method and circuit of monitoring an effective age of a target circuit are provided. A standby mode is activated in the target circuit. A standby current of a first number of circuit blocks of the target circuit is measured. The measured standby current of the first number of circuit blocks is compared to a first baseline standby current of the first number of circuit blocks. Upon determining that the measured standby current of the first number of circuit blocks is below a first predetermined factor of a baseline standby current of the first number of circuit blocks, the first number of circuit blocks is identified to have a bias temperature instability (BTI) degradation concern.

Dynamic predictor of semiconductor lifetime limits

Methods and systems for measuring a duty cycle of a signal include applying a first branch of an input signal directly to a latch. A delay of a second branch of the input signal is incrementally increased, with the second branch being applied to the latch, until the latch changes its output. A delay, corresponding to the latch's changed output, is divided by a period of the input signal to determine a duty cycle of the input signal.

Duty cycle measurement

A computer-implemented method for analyzing customer satisfaction is presented. The computer-implemented method may include capturing visual images related to individuals and order consumables, determining, by a processor, at least one measurable metric to predict variations indicating different satisfaction levels, and dynamically refining parameters if the variations exceed one or more thresholds. The computer-implemented method further includes receiving the captured visual images of the individuals and the order consumables by least one camera in communication with the processor.

Analytics to determine customer satisfaction

An electronic apparatus for testing an integrated circuit (IC) that includes a ring oscillator is provided. The apparatus configures the ring oscillator to produce oscillation at a first frequency and configures the ring oscillator to produce oscillation at a second frequency. The apparatus then compares the second frequency with an integer multiple of the first frequency to determine a resistive voltage drop between a voltage applied to the IC and a local voltage at the ring oscillator. The ring oscillator has a chain of inverting elements forming a long ring and a short ring. The ring oscillator also has an oscillation selection circuit that is configured to disable the short ring so that the ring oscillator produces a fundamental oscillation based on signal propagation through the long ring and enable the short ring so that the ring oscillator produces a harmonic oscillation based on a signal propagation through the short ring and the long ring.

Ring oscillator structures to determine local voltage value

A method and system of monitoring a reliability of a semiconductor circuit are provided. A current consumption of a first ring oscillator that is in static state is measured at predetermined intervals. Each measured current consumption value is stored. A baseline current consumption value of the first ring oscillator is determined based on the stored current consumption values. A latest measured current consumption value of the first ring oscillator is compared to the baseline current consumption value. Upon determining that the latest measured current consumption value is above a threshold deviation from the baseline current consumption value, the first ring oscillator is identified to have a dielectric breakdown degradation.

Dielectric breakdown monitor

A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

Non-destructive analysis to determine use history of processor

A software signature transceiver includes a signature receiver configured to couple to a programmable electronic device and sense a signature signal generated by the programmable electronic device, wherein the signature signal varies according to computer program codes executed by the programmable electronic device, and a signature transmitter operably connected to the signature receiver, the signature transmitter configured to transmit a signature transmission signal corresponding to the signature signal. A corresponding method to use the software signature transceiver and a software monitoring device to determine whether unknown software is executing on a programmable electronic device is also disclosed herein. A corresponding system comprising the programmable electronic device, the software signature transceiver, and a software monitoring device is also disclosed herein.

Remote monitoring of software

A method for gaining access beyond a restricted access gateway includes an access key sequence stored on memory of a device. The access key sequence includes a sequence of key entries and key touch movements. An entered request sequence including keys activated by touch on a keyboard of the device and directions of touch movements made on the keyboard is recorded. With an access controller, it is determined whether the recorded entered request sequence matches the access key sequence. Access beyond the restricted access gateway is granted to functions when the recorded entered request sequence matches the access key sequence.

Touch movement activation for gaining access beyond a restricted access gateway

Methods and circuits for monitoring circuit degradation include measuring degradation in a set of on-chip test oscillators that vary according to a quantity that influences a first type of degradation. A second type of contribution to the measured degradation is determined by extrapolating from the measured degradation for the plurality of test oscillators. The second type of contribution is subtracted from the measured degradation at a predetermined value of the quantity to determine the first type of degradation for devices represented by the predetermined value.

On-chip combined hot carrier injection and bias temperature instability monitor

Over at least part of a lifetime of a product circuit, quiescent current to a product circuit is periodically measured. Over the part of the lifetime of the product circuit, voltage to the product circuit is periodically adjusted based on the monitored quiescent current. Methods, apparatus, and computer program product are disclosed. A calibration procedure may also be performed as part of manufacturing the product circuit, in order to provide values for the quiescent current and corresponding voltage to which the voltage should be adjusted.

Autonomic supply voltage compensation for degradation of circuits over circuit lifetime

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Sleepy Hollow, NY, United States of America

Keith Aelwyn Jenkins