Intel Corporation

Other

Keith A Jones

Vui Yong Liew

Huimin Chen

Sankaran M Menon

Ronald W Swartz

Enrico David Carrieri

Matthew Hartford

John L Baudrexl

John Zurawski

Daniel R Pfunder

John W Kitterman

Warren Bosket, Sr

Kristan K Wiseley

Wai Mun Ng

Subinlal Pk

Thomas A Lyda

An Automated Dynamic low voltage monitoring (LVM) based Low-Power (ADLLP) debug capability for a system-on-chip (SoC) as well as the open/closed-chassis platform for faster TTM (Time to Market) of the final platform or system. ADLLP Debug is achieved by detection of the probe connection between a target system (e.g., SoC) and debug host system. A user can dynamically override the power, clocks and LVM for intellectual property (IP) blocks not part of the debug trace by instructing a Power Management Controller (PMC) via the Inter Processor Communication (IPC) mailbox (or any other suitable mailbox driver) to set the registers in a Target Firmware (TFW) based on the probe and debug use-case.

Techniques to enable integrated circuit debug across low power states

A seal assembly includes a tensionable annular member and a gap seal annular member that are axially juxtaposed and configured to be carried by one of a pair of coaxially movable components for sealingly engaging another one of the pair of components. The tensionable annular member includes first and second radial surfaces, an inner surface, and an outer contact surface. Rounded bottom grooves are formed across the first radial surface from the outer contact surface to the inner surface. In another embodiment, notches are formed across the inner surface from the first radial surface to the second radial surface.

Piston ring seals

A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.

JTAG scans through packetization

A first state of an interconnect protocol is entered. A particular signal is sent according to the protocol to a device over a link. During the first state, it is detected that a response to the particular signal is received in the first state. It is determined that the device supports a configuration mode outside the protocol based on the received response. The configuration mode is entered based on the response. One or more in-band configuration messages are sent within the configuration mode.

In-band configuration mode

Protective chair cover

Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the test input data, such as JTAG-compliant testing. This is facilitated, in part, via use of a bridge and one or more DFx handlers, with the bridge operating as an interface between the DFx handlers and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface. The techniques enable testing such as JTAG testing to be performed on fully-assembled devices and systems without requiring the use of dedicated test or debug ports.

Packetizing JTAG across industry standard interfaces

Growing community of inventors

Dupont, WA, United States of America

Keith A Jones