Intel Corporation

Keith A Bowman

James W Tschanz

Vivek K De

Shih-Lien L Lu

Nam Sung Kim

Tanay Karnik

Janice C Lee

Christopher B Wilkerson

Jaydeep P Kulkarni

Chris Wilkerson

Carlos Alfonso Tokunaga

James Tachanz

Tanay Karnlk

Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Sequential circuit with error detection

The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

Resilient register file circuit for dynamic variation tolerance and method of operating the same

An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single-transition DC-stressed path delay; and therefore enables the adjustment of the frequency of the dock signal to correspond to an amount or effect of the delay.

Self-contained, path-level aging monitor apparatus and method

Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.

Delay fault detection using latch with error sampling

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Hillsboro, OR, United States of America

Keith A Bowman