Micron Technology Incorporated

Keith A Benjamin

Thomas Dougherty

Nathan A Eckel

An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.

Channelization of pseudo-random binary sequence generators

A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.

Sequencer chaining circuitry

A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

Memory sub-system self-testing operations

A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.

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Blaine, MN, United States of America

Keith A Benjamin