Oki Electric Industry Co., Ltd.

Oki Data Corporation

Lapis Semiconductor Co., Ltd.

Keitaro Ishida

Takashi Kobayashi

Kazuya Yamamoto

Keisuke Watanabe

Teruaki Uehara

Keisuke Iwahashi

Yasushi Yamawaki

A memory control device includes a memory control part that controls memory through an interface part in accordance with a predetermined communication regulation, an illegal access detection part that detects an illegal access to the memory according to an access state from the memory control part to the memory and a signal state of the interface part, and a signal control part that switches the signal state of the interface part from a write-allowed state, in which the interface part is able to be written, to a write-inhibited state, in which the interface part is protected from being rewritten, when the illegal access is detected by the illegal access detection part.

Memory control device, memory device and image forming apparatus

An image data transfer circuit and an image data transfer method capable of exception processing without affecting image data of normal frames when an error is detected in image data. Image data applied to an input processing section is filtered by a filter, stored in an FIFO buffer, and sequentially read from an output section for transfer to the outside. In this event, two frame counters count numbers of frames which are being processed in input processing and output processing, respectively. When an error is detected in the input processing section, a stop controller does not output a stop request signal if the two count values do not match, and outputs the stop request signal at the time the two count values match. In this way, operations on error data are stopped after all image data of normal frames stored in the FIFO buffer has been transferred to the outside.

Image data transfer circuit

A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2&#x2212;1.

Computation circuit having dynamic range extension function

Growing community of inventors

Tokyo, Japan

Keitaro Ishida