Panasonic Corporation

Matsushita Electronics Corporation

Matsushita Electric Industrial Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Co., Ltd.

Keita Takahashi

Hiroyuki Doi

Yasushi Okuda

Nobuyuki Tamura

Masafumi Doi

Koji Yoshida

Masatoshi Arai

Kazuyuki Kouno

Nobuyoshi Takahashi

Masayoshi Nakayama

Yoshiya Moriyama

Yuji Harada

Fumihiko Noro

Yasuo Murakuki

Reiji Mochida

Takahiko Hashidzume

Takanori Ueda

Miyuki Ootomo

Yousuke Hamada

Yuriko Ishitobi

Yukihiro Yamashita

Yuichiro Higuchi

Koichi Kawashima

Kiyoshi Kurihara

A partition member for total heat exchange element () includes an ultrafine fiber portion () on a porous sheet (). The ultrafine fiber portion () is impregnated with or coated with a moisture permeable substance (), and water-insolubilized.

Partition member for total heat exchange element, total heat exchange element using this member, and total heat exchange type ventilation device

A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

Nonvolatile semiconductor storage device including cell transistor performance measuring cells

A memory array includes a resistive memory cell array having a first cell transistor and a resistance change element connected in series and a reference cell array having a second cell transistor and a resistance element connected in series. The second cell transistor of the reference cell array is connected to a reference source line, and the resistance element is connected to a reference bit line. A dummy memory cell is connected to the reference bit line in the memory cell array, and both ends of a resistance change element of the dummy memory cell are short-circuited through the reference bit line.

Nonvolatile semiconductor memory device

A reference voltage generator includes a first transistor and a second transistor coupled in series between a current supply and ground. Gate insulating films of the first transistor and the second transistor are made of the same type of film with the same thickness. Impurities contained in gate electrodes of the first transistor and the second transistor have different conductivity types, or have the same conductivity type and different concentrations. The first transistor has a greater gate width than the second transistor. The first transistor and the second transistor operate in a subthreshold region when a reference voltage is output outside.

Reference voltage supply circuit

The protection element of the present invention is constructed of a MOS capacitor composed of a semiconductor substrate, an insulating film formed on the semiconductor substrate and a word line formed on the insulating film. A well region having a conductivity type opposite to that of the semiconductor substrate is formed in a portion of the semiconductor substrate constituting the MOS capacitor. If charge exceeding the breakdown voltage of the insulating film constituting the MOS capacitor is induced in the word line, the induced charge is released into either the semiconductor substrate or the well region depending on whether the induced charge is positive or negative.

Protection element and fabrication method for the same

A semiconductor memory device has an element isolation region between rewrite units of memory cells. A plurality of memory cells are memory cell groups arranged in a row direction, and each memory cell group consists of (8&#xd7;N) memory cells arranged in a row direction as a unit to be used as a storage region. The number of a plurality of selection word lines is at least eight, and the number of selection transistors corresponding to at least N is connected to each of the plurality of selection word lines. At least one selection transistor in addition to (8&#xd7;N) selection transistors are connected in total to the plurality of selection word lines. A plurality of main bit lines includes at least one main bit line in addition to (4&#xd7;N) main bit lines connected to the common drain of a pair of selection transistors.

Memory device having additional selection transistors and main bit lines

First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.

Method for fabricating semiconductor device

The semiconductor memory device includes: a first well of a first conductivity type, a second well of the first conductivity type and a third well of a second conductivity type formed in a substrate: a diffusion bit line extending in a row direction and a word line extending in a column direction both formed in the second well; a plurality of semiconductor memory elements arranged in a matrix, each connected with the diffusion bit line and the word line; a selection transistor formed in the first well for applying a voltage to the diffusion bit line; and a forward diode formed of a diffusion layer of the first conductivity type formed in the third well and the third well. The diffusion bit line, the forward diode and the source of the selection transistor are electrically connected with one another.

Semiconductor memory device and driving method for the same

A semiconductor device includes a protection target element formed on a semiconductor substrate and includes a protection target element electrode, a substrate connecting part including a substrate connecting electrode electrically connected to the semiconductor substrate and a fuse structure provided between the protection target element electrode and the substrate connecting electrode and includes a fuse film configured to be torn by applying a predetermined current thereto. The protection target element electrode, the substrate connecting electrode and the fuse film are formed of an integral conductive film as long as the fuse film is not torn.

Semiconductor device and method for manufacturing the same

A nonvolatile semiconductor memory device includes bit line diffusion layers extending along the X direction in an upper portion of a semiconductor substrate; and gate structures extending along the Y direction on the semiconductor substrate and each including a charge trapping film and a gate electrode. The nonvolatile semiconductor memory device further includes a first interlayer insulating film in which first contacts respectively connected to the bit line diffusion layers are formed; and second contacts that penetrate through a UV blocking film and a second interlayer insulating film formed on the first interlayer insulating film and have bottom faces respectively in contact with the first contacts and top faces respectively in contact with metal interconnections.

Nonvolatile semiconductor memory device and method for fabricating the same

A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS.

Semiconductor protection circuit, method for fabricating the same and method for operating semiconductor protection circuit

A nonvolatile semiconductor memory device includes: a gate dielectric made of a multilayer dielectric that is formed on a substrate and discretely accumulates charges; a gate electrode formed on the gate dielectric; a pair of diffusion regions formed in the surface of the substrate with the gate electrode interposed therebetween and serving as a source and a drain; and a channel region existing between the diffusion regions. At least one of regions of the gate dielectric located between the pair of diffusion regions and lateral end parts of the gate electrode opposed to the diffusion regions includes a fixed charge accumulation region in which charges produced by irradiating the gate electrode with ultraviolet light can be accumulated, and at least one said diffusion region located below the fixed charge accumulation region is formed to overlap with the fixed charge accumulation region in plan configuration and extend beyond the fixed charge accumulation region toward the middle of the channel region in plan configuration.

The fabrication method for a nonvolatile semiconductor memory device having a memory cell area including memory cells and a peripheral circuit area adjacent to the memory cell area and including peripheral transistors, the method including the steps of: (1) forming a first active region in the memory cell area and a second active region in the peripheral circuit area in a substrate by forming isolation insulating films in the memory cell area and the peripheral circuit area so as to be away from a boundary therebetween; (2) forming a bottom insulating film and an intermediate charge trap film sequentially over the entire surface of the substrate; (3) removing a portion of the intermediate charge trap film formed in the peripheral circuit area using a first mask film; (4) forming a gate insulating film in the peripheral circuit area and also at least part of a top insulating film in the memory cell area; (5) forming a gate electrode film on the top insulating film and the gate insulating film; and (6) forming gate electrodes of memory cells and peripheral transistors by patterning the gate electrode film. The step (3) includes a step of aligning an end of the first mask film with the boundary in the substrate.

Nonvolatile semiconductor memory device and fabrication method for the same

A semiconductor memory device includes: a memory cell array region formed in a semiconductor region of a first conductivity type and having a plurality of memory cells arranged in rows and columns; a plurality of word lines each of which collectively connects ones of the plurality of memory cells aligned in the same row; and a protective diode region formed in the semiconductor region to be separated from the memory cell array region. In the protective diode region, a protective diode element is constructed by making a junction between a first diffusion layer of a second conductivity type formed in the upper portion of the semiconductor region and the semiconductor region. Each of the word lines extends to the protective diode region and is brought into direct connection to the first diffusion layer of the second conductivity type, thereby making electrical connection to the protective diode element.

Semiconductor memory device and method for manufacturing the same

A semiconductor memory is provided with memory cells including bit lines made of a diffusion layer formed in a semiconductor substrate, charge-trapping gate insulating films formed between the bit lines and word lines formed on the gate insulating films. An interlayer insulating film is formed over the memory cells and bit line contact plugs are formed in the interlayer insulating film to be connected to the bit lines. Further, a light blocking film is formed on at least part of the interlayer insulating film covering the memory cells and part of the light blocking film formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film in the neighborhood of the bit line contact plugs.

Growing community of inventors

Nara, Japan

Keita Takahashi