Renesas Electronics Corporation

Keisuke Tsukamoto

Tatsuyoshi Mihara

Mikio Tsujiuchi

Yosuke Takeuchi

Tatsunori Murata

Ryoji Matsuda

Masamichi Matsuoka

Shinya Hirano

Yuichiro Fujiyama

A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Method of manufacturing a semiconductor device

The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.

Semiconductor device

To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed over the bottom electrode so as to cover the MTJ element part, wherein the bottom electrode is formed by amorphized metal nitride and the protection film is formed by an insulating film containing nitrogen.

Semiconductor device including a magnetic tunnel junction and method of manufacturing the same

There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a lower electrode, a magnetoresistive element, an upper electrode, and a protective film. The lower electrode is formed over the semiconductor substrate. The magnetoresistive element includes a fixed layer, a tunneling insulating film, and a free layer. The upper electrode is disposed over the free layer. The protective film covers the sides intersecting the main surfaces of the lower electrode, the fixed layer, the tunneling insulating film, the free layer, and the upper electrode. The fixed layer, whose magnetization direction is fixed, is disposed over the lower electrode. The tunneling insulating film is disposed over the fixed layer. The free layer, whose magnetization direction is variable, is disposed over a main surface of the tunneling insulating film. The width of the upper electrode is smaller than that of each of the lower electrode and the fixed layer.

Semiconductor device and manufacturing method of semiconductor device

To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element.

Growing community of inventors

Kanagawa, Japan

Keisuke Tsukamoto