Renesas Technology Corp.

Keisuke Tsukamoto

Daisuke Okada

Tsutomu Okazaki

Yoshihiro Ikeda

Hiroshi Yanagita

Shoji Shukuri

Tatsuya Fukumura

Koji Kishi

Keiichi Haraguchi

Defects in element forming regions on which memory cells of a non-volatile memory are formed are to be diminished to reduce leakage current. End portions of element forming regions with non-volatile memory cells formed thereon are extended a length D by utilizing the region which underlies a dummy conductive film, whereby a stress induced from an insulating film which surrounds the element forming regions is concentrated on the extended region. As a result, defects do not extend up to the regions where memory cells are formed and therefore it is possible to reduce leakage current in the memory cells.

Semiconductor device with reduced memory leakage current

At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage gate insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric film of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.

Method of manufacturing a semiconductor device having trenches for isolation and capacitor formation trenches

Semiconductor integrated circuit device having a dummy conductive film and method of manufacturing the same

An insulating film for protecting an upper portion of a control gate electrode is constituted by a silicon oxide film, and thereby stress affecting a gate oxide film and a substrate that is located below a bottom portion thereof is reduced. Further, an etching prevention film consisting of a silicon nitride film is formed on a sidewall of the silicon oxide film, and thereby it is possible to prevent the sidewall of the silicon oxide film from being etched in a hydrofluoric acid cleaning step after processing of a gate electrode.

Semiconductor integrated circuit device and manufacturing method thereof

Growing community of inventors

Ome, Japan

Keisuke Tsukamoto