Hrl Laboratories, LLC

Teledyne Scientific and Imaging, LLC

The Boeing Company

Keisuke Shinohara

Miroslav Micovic

Andrea Corrion

Dean C Regan

David F Brown

Alexandros Margomenos

Hooman Kazemi

Shawn D Burnham

Miguel Urteaga

Peter J Willadsen

Hasan Sharifi

Casey King

Rongming Chu

Wonill Ha

Paul B Hashimoto

Colleen M Butler

Karim S Boutros

Sameh G Khalil

Ivan Milosavljevic

Joel C Wong

Yan Tang

Eric Regan

Hector L Bracamontes

David T Chang

James Chingwei Li

Pamela R Patterson

Tahir Hussain

Jongchan Kang

Charles McGuire

Richard L Pierson, Jr

Adam J Williams

Robert G Nagele

Dana C Wheeler

Mary C Montes

Jason W May

Bruce T Holden

Ara K Kurdoghlian

Avijit Bhunia

Ya-Chi Chen

Andy Carter

Ivan Alvarado-Rodriguez

Helen Hor Ka Fung

Sameh Khalil

Laterally-gated transistors and lateral Schottky diodes are disclosed. The FET includes a substrate, source and drain electrodes, channel, a gate electrode structure, and a dielectric layer. The gate electrode structure includes an electrode in contact with the channel and a lateral field plate adjacent to the electrode. The dielectric layer is disposed between the lateral field plate and the channel. The lateral field plate contacts the dielectric layer and to modulate an electric field proximal to the gate electrode proximal to the drain or source electrodes. Also disclosed is a gate electrode structure with lateral field plates symmetrically disposed relative to the gate electrode. Also disclosed in a substrate with dielectric structures buried in the substrate remote from the gate electrode structure. A lateral Schottky diode having an anode structure includes an anode (A), cathodes (C) and lateral field plates located between the anode and the cathodes.

Laterally-gated transistors and lateral Schottky diodes with integrated lateral field plate structures

An ohmic contact for a multiple channel FET comprises a plurality of slit-shaped recesses in a wafer on which a multiple channel FET resides, with each recess having a depth at least equal to the depth of the lowermost channel layer. Ohmic metals in and on the sidewalls of each recess provide ohmic contact to each of the multiple channel layers. An ohmic metal-filled linear connecting recess contiguous with the outside edge of each recess may be provided, as well as an ohmic metal contact layer on the top surface of the wafer over and in contact with the ohmic metals in each of the recesses. The present ohmic contact typically serves as a source and/or drain contact for the multiple channel FET. Also described is the use of a regrown material to make ohmic contact with multiple channels, with the regrown material preferably having a corrugated structure.

Ohmic contact for multiple channel FET

A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain, wherein a two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain, wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain, and wherein the 2DEG decreases in density in the drift region between the gate and the drain.

HEMT GaN device with a non-uniform lateral two dimensional electron gas profile and method of manufacturing the same

A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Monolithic integration of group III nitride epitaxial layers

A FET with a buried gate structure. The FET's gate electrode comprises a plurality of buried gate structures, the tops of which extend above the substrate's top surface and the bottoms of which are buried to a depth at least equal to that of the bottom of the channel layer, or the 2DEG plane within a channel layer for a HEMT, such that the buried gate structures contact the channel layer only from its sides. A head portion above and not in contact with the substrate's top surface contacts the tops of and interconnects all of the buried gate structures. Drain current is controlled by channel width modulation by lateral gating of the channel layer by the buried gates structures. The FET may include at least one field plate which comprises a slit structure in which the field plate is divided into segments.

FET with buried gate structure

A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

FET with micro-scale device array

Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.

Fabrication of microfluidic channels in diamond

A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer includes a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain. A two dimensional electron gas (2DEG) has a non-uniform lateral distribution in the drift region between the gate and the drain.

Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.

T-gate field effect transistor with non-linear channel layer and/or gate foot face

An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dialectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Flexible electronic circuit and method for manufacturing same

A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Stepped field plate wide bandgap field-effect transistor and method

A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Monolithic integration of GaN and InP components

An electronic circuit comprising: an integrated circuit chip, the integrated circuit chip having a top face; portions of the top face of the chip being covered by a first metal layer electrically connected to the integrated circuit; and a dielectic layer formed on the top face of the chip beside and on top of said first metal layer; wherein the dielectric layer extends parallel to the top face of the chip beyond the edges of the chip, the first metal layer extending in the dielectric layer beyond the edges of the chip; and wherein portions of a top surface of the dielectric layer are covered by a second metal layer, portions of the first and second metal layers being electrically connected through the dielectric layer.

Growing community of inventors

Thousand Oaks, CA, United States of America

Keisuke Shinohara