Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Keisuke Sakai

Masayuki Toyama

Toshiyuki Honda

Takaharu Yoshida

Toshiki Mori

Seiji Yamahira

Yasuhiro Tomita

Tetsushi Kasahara

Takayuki Tanaka

Makoto Matsumoto

Manabu Inoue

Shinji Inoue

Takuji Maeda

Masahiro Nakanishi

Tomoaki Izumi

Kazuaki Tamura

Kiminori Matsuno

Shouichi Tsujita

Teruo Akashi

Yoshida Takaharu

Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories.

Voltage control circuit for providing two voltages generated based on a parameter corresponding to an input signal

Process execution control based on the internal states of flash memories and power supply circuit information

A communication system in which an operating voltage can be selected from a plurality of interface voltages enables an interface voltage to be switched in a stable manner during operation of the system. When the interface voltage is to be switched, a host device () and a slave device () perform the switching while maintaining the signal level of buses in a stable manner. This structure enables the communication system to switch an interface voltage using a small number of signal lines.

Interface device for host device, interface device for slave device, host device, slave device, communication system and interface voltage switching method

When a file system control partA writes file data into a main memorya file can be easily written continuously and the number of file copy can be decreased at updating a directory entry by writing the file data and a directory entry into different allocation units. In this manner, when using a nonvolatile memory in which physical block size as an erase unit is larger than cluster size, the write performance can be enhanced.

Nonvolatile memory system, nonvolatile memory device, memory controller, access device, and method for controlling nonvolatile memory device

A control method of a non-volatile memory apparatus, which can execute data writing normally after the next startup even when a process is interrupted because of the occurrences of abnormal conditions such as power shut down during data writing or data erasing is provided. The control method of a non-volatile memory apparatus of the present invention comprises: a first flag writing step of writing a fixed value, which indicates that data is written, on a first flag existing in a redundancy area on a first page of a physical block and indicating whether or not data is written on the first page; and a data writing step of writing data on the physical block, when the data is written on the non-volatile memory consisting of a plurality of physical blocks.

Control method of a non-volatile memory apparatus

A memory card () is comprised of: a flash memory () that includes a plurality of physical blocks () made up of a plurality of pages for storing data and a page register () that holds data to be written to a page; and a controller () that specifies and erases an invalid physical block with reference to a valid block table () indicating whether valid data is stored in each of the physical blocks (), when data is written, and that transfers, at the same time, the data to be written to the page register () while carrying out said erasure.

Non-volatile storage device and control method thereof

To provide a nonvolatile storage device and control method thereof which improve convenience of portable devices by shortening initialization time. In generating a data validity table at initialization, a control part firstly reads out a validity flag and a second translation table. In the case where the validity flag is valid, logical blocks in the second translation table are valid. For that reason, the fourth table generation means can set all logical blocks in the second translation table as being valid, in the data validity table. In a single reading as mentioned above, the fourth table generation means can carry out setting with respect to a plurality of logical blocks. Further, with respect to a partial logical block which is set as being valid in the data validity table, it is possible to bypass reading out the data validity flag of the block and proceed to operation of next partial logical block.

Growing community of inventors

Kyoto, Japan

Keisuke Sakai