Mitsubishi Denki Kabushiki Kaisha

Vlsi Technology Research Association

Keisuke Okada

Sumitaka Takeuchi

Masatoshi Kimura

Tetsuya Matsumura

Masahiko Yoshimoto

Tetsuo Tada

Hiroyuki Kouno

Masao Nakaya

A data generating apparatus for sequentially generating data includes a binary counter, a setting circuit, a match detecting circuit, and a selector group. The binary counter responds to a clock signal for sequentially generating data. The setting circuit sets a data preceding the data to be skipped. The match detecting circuit detects a match of the data set by the setting circuit with the data generated by the binary counter. The selector group supplies '1' to the binary counter when a match is not detected by the match detecting circuit, and '2' to the binary counter when a match is detected by the match detecting circuit. The binary counter adds '2' to the preceding data when a match is detected by the match detecting circuit to skip the desired data.

Data generating apparatus generating consecutive data and having a data

A DRAM having a data preset function is disclosed. A memory cell includes connectors which are formed of contact holes or through holes and which can be selectively formed in order to program preset data. For example, when preset data '0' is programmed, connectors are formed, and connector 17 is not formed. When a data precharge signal of a high level is applied, a transistor is turned on and as a result, a data storage capacitor is discharged. In other words, predetermined data is written into capacitor. Thus, the DRAM having the data preset function is provided.

Semiconductor memory having data preset function

A decode circuit decodes digital signals X1 and X0 as multiplicand to output decoded signals A0-A3. One of these decoded signals A3-A0 is set to be logic 1 in accordance with a value of a multiplicand. A logical operation circuit includes a plurality of operation circuits. Each logical operation circuit performs an independent operation for obtaining a logical value of each bit of the digital signal which is a multiplication result, based on the decoded signals A0-A3 and the digital signals R1 and R0 as a multiplier. Therefore, a result of an operation of a certain bit does not affect results of operations of other bits, so that the logical operation of each bit can be conducted without waiting termination of the logical operations of other bits, which enables high-speed multiplications.

Digital multiplier

A binary data converter is adapted to convert a positive binary data into a negative binary data represented by a complement on two and vice verse. The conversion is effected as follows. A least significant bit of an inputted binary data is outputted as the least significant bit of the converted binary date as it is. With respect to bit signal other than the least significant bit, respective input bit signals less significant than the corresponding input bit signal are ORed. Depending on the result thereof, inverted or non-inverted signals of the corresponding input bit signals are outputted as the bit signals of the converted binary data. Therefore, carry delay is not generated, and thus the operation speed can be increased. Further, the simple circuit structures can reduce the number of required elements.

Binary data converter

An updown counter up-counts binary data stored in respective flip-flops in an up-count mode, and down-counts the binary data stored in the respective flip-flops in a down-count mode. When a command for an up-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on two after converting it into a complement on one. When a command for a down-count mode is applied by an up/down control signal, the binary data stored in the respective flip-flops is converted into a complement on one after converting it into a complement on two. The converted data is used to rewrite the data stored in the respective flip-flops.

Up/down counter for counting binary data stored in flip flops

An input analogue signal is converted to a two-valued signal and then it is supplied to each encoder. Each gate signal forming circuit forms a gate signal based on an input digital signal. Each encoder encodes the above stated two-valued signal, an encoding function thereof being determined based on the above stated gate signal. As a result, each encoder outputs a result of multiplication of the two-valued signal and the digital signal in the form of a binary digital signal.

Digital finite impulse response filter and method

A semiconductor integrated circuit which is comprised of the following; a plurality of comparators which respectively compare analog values inputted for multiplication with individual reference voltages respectively, multiplication means which controls values outputted from those plural comparators by applying signals corresponding to digital values inputted for multiplication and outputs the product of the values outputted from those plural comparators and the digital values, and a complement operation circuit which converts the value outputted from multiplication means into complement when the digital value is negative.

A/D converter having multiplication function

An A/D converter of a serial-parallel comparison type has both multiplying functions of an analog input data and a digital input data. The analog input data V.sub.X is converted into a digital code I.sub.c corresponding to two more significant digits, by a first parallel comparing portion and a first determining circuit, and converted into a digital code I.sub.f corresponding to two less significant digits by a second parallel comparing portion and a second determining circuit. The digital codes I.sub.c and I.sub.f are alternately applied to a control circuit by a first selector circuit. Two more significant bits R.sub.c and two less significant bits R.sub.f of a 4-bit digital input data are respectively applied to a control signal generating circuit by a second selector circuit. Multiplications of R.sub.c I.sub.c, RfIc, R.sub.c I.sub.f and R.sub.f I.sub.f are serially performed within the time period of one conversion by the control signal generating circuit and the control circuit. The multiplied results are shifted four bits, two bits, two bits and 0 bits, respectively, and then, added to each other. As a result, the product of the analogue input data and the digital input data is calculated.

A/D converter comprising encoder portion having function of multiplying

A semiconductor integrated circuit so arranged that selection is made out of output signals of a decision circuit which determines the levels of analog values inputted as an object for multiplication and multiplication is carried out with respect to the selected signal and the digital value inputted as an object for multiplication, the result of the multiplication being added with the digital value as shifted to the higher position of specified bits, a multiplication result being thereby calculated with respect to the analog value and the digital value, whereby the required area of wiring connections is reasonably reduced and faster operation is assured.

Semiconductor integrated circuit for multiplying analog and digital

A semiconductor integrated circuit includes a plurality of comparators for comparing an analog input with reference voltage or voltages, holding means for holding a digital value, and control means for controlling the outputs of the plurality of comparators by a control signal responsive to the digital value to output the multiplication result of the output values of the plurality of comparators and the digital value. Thus, the integrated circuit can construct a circuit having functions of an A/D converter and a multiplier on one chip.

A wafer testing device in which a plurality of wafers can be tested simultaneously significantly reducing the time required for testing each chip. A prober is provided which receives a wafer to be tested. A probe card is coupled to the prober having a window through which a plurality of semiconductor memory chips on the wafer are observable. A plurality of probes are coupled to the periphery of the window in such a manner that the probes can be brought into contact with bonding pads on the plurality of semiconductor memory chips. A tester is connected to the probes which is capable of simultaneously testing each of the plurality of chips.

Semiconductor testing device

A capacitive element of a semiconductor integrated circuit comprising a first conductor provided in the input side and a second conductor provided in the output side further includes a third conductor to be connected with the first conductor. The front and back surfaces of the second conductor are entirely covered by the first and third conductors. Portions connecting the first and third conductors are arranged along the peripheral edge portions of the second conductor excepting a signal extracting portion.

Growing community of inventors

Hyogo, Japan

Keisuke Okada