Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Other

Skhynix Inc.

Keisuke Nakatsuka

Tomoya Sanuki

Yasuhito Yoshimizu

Fumitaka Arai

Takashi Maeda

Toshio Fujisawa

Shinya Arai

Shinichi Kanno

Takashi Fukushima

Keiji Hosotani

Masayuki Miura

Nobuyuki Momo

Tatsuro Hitomi

Arata Inoue

Yasunori Iwashita

Hideaki Aochi

Ryota Katsumata

Tsuneo Inaba

Katsuhiko Hoya

Yoshitaka Kubota

Tetsuaki Utsumi

Yoshiro Shimojo

Go Shikata

Hiroaki Ashidate

Yasuhiro Uchiyama

Naoya Yoshimura

Hiroshi Maejima

Tatsuya Kishi

Takeshi Hamamoto

Kenichiro Yoshii

Hiroyuki Kanaya

Satoshi Inaba

Satoshi Nagashima

Hiroki Sasaki

Tadashi Miyakawa

Katsuyuki Fujita

Hisanori Aikawa

Hiroyuki Takenaka

Yoshinori Kumura

Masayoshi Tagami

Hiroshi Nakaki

Motoyuki Sato

Shigeru Kawanaka

Kazumasa Sunouchi

Masaru Toko

Yutaka Shirai

Hideto Horii

Hideo Wada

Takahiro Tomimatsu

Shintaro Sakai

Jae Yun Yi

Motohiko Fujimatsu

Ryo Tanaka

Keita Hasegawa

Takuya Ohoka

Daisuke Fujiwara

Hong Ju Suh

Se Dong Kim

A semiconductor memory device includes first and second memory cell arrays. The first array includes a first semiconductor portion, extending in a first direction, on which a first memory cell and a first select transistor are formed, a first word line connected to the first cell, a first select gate line connected to the first transistor, and a first bit line connected to the first semiconductor portion. The second array includes a second semiconductor portion, extending along the first direction, on which a second memory cell and a second select transistor are formed, a second word line connected to the second cell, a second select gate line connected to the second transistor, and a second bit line connected to the second semiconductor portion. The first and second word lines are electrically connected, but the first and second select gate lines are not electrically connected.

Semiconductor memory device

A method of manufacturing a semiconductor device includes forming a first metal pad in each of a plurality of first regions on a first substrate so that warpage is generated on the first substrate. The method further includes forming a second metal pad in each of a plurality of second regions on a second substrate via a predetermined pattern. The method further includes bonding, after forming the first metal pad and the second metal pad, the first substrate with the second substrate. Moreover, the method further includes: making a correction, at a time of forming the predetermined pattern in each of the plurality of second regions on the second substrate, to change a position of the predetermined pattern in each of the plurality of second regions in a direction of being closer to a center of the second substrate for a first direction and to change the position of the predetermined pattern in a direction of being farther from the center of the second substrate for a second direction.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first stacked body and a second stacked body bonded to the first stacked body. The first stacked body includes a first pad provided on a first bonding surface to which the first stacked body and the second stacked body are bonded. The second stacked body includes a second pad bonded to the first pad on the first bonding surface. When a direction from the first stacked body to the second stacked body is defined as a first direction, a direction intersecting with the first direction is defined as a second direction, a direction intersecting with the first direction and the second direction is defined as a third direction, dimensions of the first pad and the second pad in the third direction are defined as PXand PX, respectively, and dimensions of the first pad and the second pad in the second direction are defined as PYand PY, respectively, the dimensions of the first pad and the second pad satisfy at least one of Equations (1) and (2) below.PX1>PY1  (1)PY2>PX2  (2).

Semiconductor device, wafer, and wafer manufacturing method

According to an embodiment, a semiconductor memory device includes a first memory cell array, a second memory cell array, and a row decoder. The first memory cell array includes a first select transistor, a first memory cell, a second select transistor, a first word line, a first select gate line, and a second select gate line. The second memory cell array includes, a third select transistor, a second memory cell, a fourth select transistor, a second word line, a third select gate line, a fourth select gate line. The first word line and the second word line are commonly coupled to the row decoder. The first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder.

Semiconductor memory device with plurality of arrays

According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

Storage device and control method

According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

Chip bonded semiconductor memory device with different charge storage films

A memory device includes a substrate; first conductors aligned apart from each other in a first direction; a second conductor and a third conductor each extending in a second direction between the substrate and the first conductors, and being aligned apart from each other in the second direction; fourth conductors aligned apart from each other in the first direction on an opposite side of the substrate with respect to the first conductors; a fifth conductor extending in the second direction between the first conductors and the fourth conductors; and a first interconnect coupling between the fifth conductor and the substrate. The first interconnect includes a contact extending in the first direction and passing through the first conductors between the second and third conductors.

Memory device

A semiconductor memory device includes a first chip, a second chip, and a multiple of bonding pads. The first chip has a multiple of memory pillars that penetrate a multiple of wiring layers in a first direction. The second chip is bonded to the first chip. The multiple of bonding pads are provided at a bonding face between the first chip and the second chip. The multiple of bonding pads include a first bonding pad that electrically connects a first memory pillar among the multiple of memory pillars to one of a multiple of transistors, and a second bonding pad that neighbors the first bonding pad when seen from the first direction, and which electrically connects a second memory pillar among the multiple of memory pillars to one of the multiple of transistors. The second memory pillar does not neighbor the first memory pillar when seen from the first direction.

According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

According to one embodiment, in a semiconductor memory device, the first chip has plural memory cells provided at plural intersection positions where the plural first conductive layers and the plural first semiconductor films intersect each other. The second chip has plural memory cells provided at plural intersection positions where the plural second conductive layers and the plural second semiconductor films intersect each other. A first connection configuration and a second connection configuration are insulated from each other. The first connection configuration reaches the third chip from a first conductive layer that a tip of the first semiconductor film reaches among the plural first conductive layers. The second connection configuration reaches the third chip from a second conductive layer that a tip of the second semiconductor film reaches among the plural second conductive layers.

A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Semiconductor storage device

According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

Memory system

A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

Semiconductor storage device and system

In one embodiment, a semiconductor device includes a substrate, transistors on the substrate, and a stacked film provided above the transistors, including electrode layers separated from each other in a first direction, and including first, second and third regions. The device further includes plugs provided to the electrode layers in the first region, a first columnar portion in the second region, and a second columnar portion in the third region. At least one electrode layer among the electrode layers includes a first portion in the first region, a second portion in the second region, and a third portion in the third region, and is a continuous film from the second portion to the third portion via the first portion. The transistors include first, second and third transistors provided right under the first, second and third regions and electrically connected to first, second and third plugs among the plugs, respectively.

Semiconductor device and method of manufacturing the same

A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.

Semiconductor memory device having contact plugs extend in the stacking direction of the plurality of the first and second conductive layers

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Kobe Hyogo, Japan

Keisuke Nakatsuka