Cirrus Logic Inc.

Keisuke Kato

Christopher P Zook

Tony J Yoon

Weichi Ding

Frederick Siu-Huang Au

Syed H Husaini

The invention provides a method and apparatus for generating delays to shift edges of an EFM data stream from an EFM modulator for a CD-R and CD-RW write encoder. EFM data pulse edges may be delayed in increments of about {fraction (1/32)} Tefm where Tefm is the code rate clock of an EFM data stream output. The delays are generated by a synthesizer running at four times the EFM code rate. The synthesizer may be built using a four-stage ring oscillator. Delays are selectable based upon the write strategy matrix in coarse increments of &frac14; T and fine increments of {fraction (1/32)} T. For the coarse delay, the EFM data may be passed through a four stage shift register running at Fsynth, where Tefm&equals;4&times;Fsynth, allowing for a coarse delay selection of &frac14; Tefm. The four stages of the ring oscillator provides eight phases of the synthesizer, each phase shifted by &frac18; Tsynth thereby providing a delay selection of &frac18; within each Tsynth period, translating into {fraction (1/32)} Tefm resolution. The method and apparatus of the present invention may be extended to even finer delays by increasing the number of stages in the ring oscillator. Resulting delay increments would be Tefm/(2*N*M) wherein N is defined as the number of ring oscillator stages and M is the coarse delay.

Multi-stage ring oscillator for providing stable delays on EFM data pulses for recording CD-R and CD-RW medium

An efficient error correction processor is disclosed for correcting a multi-dimensional code comprising a first set of codewords that intersect with a second set of codewords. The error correction is carried out by performing iterative passes over the first and second set of codewords. The individual codewords are corrected using error syndromes which are computed as a function of the codeword data. In the preferred embodiment, the individual codewords are encoded according to a Reed-Solomon code and the error syndromes are computed as the modulo division of the codeword polynomial by the factors of a generator polynomial. To increase the throughput of the error correction processor, a syndrome buffer is employed to facilitate generating the error syndromes for both the first and second set codewords concurrently. In this manner, after a pass over the first set of codewords, the error syndromes for the second set codewords are available for immediate processing. In one embodiment, the syndrome buffer stores the error syndromes for both the first and second set codewords so that only one pass over the codewords is necessary to generate the error syndromes. In subsequent passes, the error syndromes are available immediately; they are not regenerated as in the prior art.

Concurrent row/column syndrome generator for a product code

A CD-R controller for recording on a CD-R disk a signal representative of a set of signal data. The CD-R controller includes a buffer manager for receiving a command such as a CUE-sheet, and sends the command to a micro-controller. The micro-controller generates instructions corresponding to each command by using information stored in a ROM. The buffer manager stores the instructions in a buffer and then sends the instructions to a CD-R formatter. Buffer manager may then send signal data corresponding to the instructions to a recording circuit. CD-R formatter generates control signals to the recording circuit from the instructions. The control signals cause recording circuit to generate recording signals to a CD-R drive. The CD-R drive may record the signal representative of the signal data in response to the recording signals.

CD-R recording circuit with formatter to increase rate of generating

A header detect method and apparatus for an optical media decoder circuit includes one or more comparators which compare target header information to header information read from the optical media for a current sector and each subsequent sector until the header information read from the optical media matches the target header information. The target header information is programmed into one or more target header registers. The information stored in the target header registers is then compared to the header information read from the optical media. Multiple comparators are used, to compare the header information read from the optical media for the current sector and a number of previous sectors to the target header information programmed into each of the target header registers, in order to provide a redundancy within the system and allow the apparatus to locate the target header even if one or more of the registers contain errors. The comparators activate a match signal when the header information read from the optical disk matches the target header information. The control logic circuit will then output a sector found signal which notifies the optical media decoder that the target sector has been located. If multiple comparators are included, a system designer may program a predetermined threshold, specifying a number of match signals which must be activated before the control logic circuit outputs the sector found signal.

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Yamamoto, Japan

Keisuke Kato